From: Krzysztof Kozlowski <krzk@kernel.org>
To: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>,
Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller
Date: Tue, 21 Apr 2026 12:30:11 +0200 [thread overview]
Message-ID: <20260421-free-meticulous-beetle-bb3fcd@quoll> (raw)
In-Reply-To: <20260420034932.1247344-2-shengchao.guo@oss.qualcomm.com>
On Mon, Apr 20, 2026 at 11:49:31AM +0800, Shawn Guo wrote:
> From: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
>
> Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
> Nord SoC. It has 16 IPC channels, compared to 3 on X1E80100 CPUCP.
And more channels does not make it incompatible (see writing bindings or
DTS101 slides). Please provide explanation why devices are not
compatible.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-04-21 10:30 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 3:49 [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC Shawn Guo
2026-04-20 3:49 ` [PATCH 1/2] dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller Shawn Guo
2026-04-21 10:30 ` Krzysztof Kozlowski [this message]
2026-04-22 10:43 ` Shawn Guo
2026-04-20 3:49 ` [PATCH 2/2] mailbox: qcom-cpucp: Add support for " Shawn Guo
2026-04-20 8:22 ` Konrad Dybcio
2026-04-21 7:39 ` Shawn Guo
2026-04-20 8:23 ` [PATCH 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC Konrad Dybcio
2026-04-21 7:38 ` Shawn Guo
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