Re: [PATCH RFC 0/4] arm64: rockchip: The hunt for exact pixel clocks on RK3576

[Maxime Ripard <mripard@kernel.org>]

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Hi Brian, Alexey,

On Mon, Apr 20, 2026 at 12:02:58PM -0400, Brian Masney wrote:
> On Sat, Apr 18, 2026 at 12:24:57AM +0200, Sebastian Reichel wrote:
> > On Fri, Apr 17, 2026 at 07:11:43PM +0400, Alexey Charkov wrote:
> > > Dear all,
> > > 
> > > Need the help of the collective wisdom of the community.
> > > 
> > > The problem I'm trying to solve is reliably obtaining the exact pixel
> > > clock for arbitrary display modes supported by the RK3576 SoC.
> > > 
> > > Rockchip RK3576 has three display output processors VP0~VP2, each
> > > supporting different ranges of display modes, roughly as follows:
> > > - VP0: 4K 120Hz
> > > - VP1: 2.5k 60Hz
> > > - VP2: 1080p 60Hz

Do any of those have an additional multiplier or divider after the PLL?

I'm asking because 4k@120Hz is 1188MHz, and 1080p@60Hz is 148.5 (so 1188
/ 8). 2.5k @ 60 might be a bit more problematic, but my point is that
for HDMI/DP, most resolutions all have a pixel clock that are multiples
of 148.5MHz.

If you manage to get the PLL to the highest you need (1188MHz), and then
apply dividers, you don't need to change the PLL frequency anymore.

> > > Each one obviously needs a pixel clock. The required frequencies for the
> > > pixel clocks vary greatly depending on the display mode, and need to be
> > > matched within a tight tolerance, or else many displays will refuse to
> > > work. E.g. the preferred (maximum) display mode out of VP1 is particularly
> > > awkward, because it requires a pixel clock of 248.88 MHz, which cannot
> > > be obtained using integer dividers from its default clock source (GPLL
> > > at 1188 MHz), and the nearest approximation is 237.6 MHz, which is well
> > > outside the tolerance of e.g. DP specification, resulting in a blank
> > > screen on most displays by default.
> > > 
> > > The clock sources are of course configurable, in particular there are muxes
> > > connected to each VP for selecting the source of the pixel clock:
> > > - Each VP can take the clock either from the (single!) HDMI PHY or from
> > >   its dedicated dclk_vpX_src mux
> > > - The dclk_vpX_src mux can select the clock from a number of system PLLs
> > >   (GPLL, CPLL, VPLL, BPLL, LPLL)
> > > 
> > > While the system PLLs can be configured to output a wide range of
> > > frequencies, they are shared between many system components. E.g. on the
> > > current mainline kernel on one of my RK3576 boards I've got the following:
> > > GPLL: 1188 MHz, enable count 20
> > > CPLL: 1000 MHz, enable count 17
> > > VPLL: 594 MHz, enable count 0 (yaay!)
> > > BPLL, LPLL: 816 MHz, enable count 0 (but these last ones don't have
> > >             predividers, so are less flexible)
> > > 
> > > So ultimately there is exactly one free fractional PLL (VPLL) which can be
> > > used to generate arbitrary pixel clocks, but we have up to three consumers
> > > trying to drive different display modes from it (e.g. HDMI on VP0, DP on
> > > VP1 and MIPI DSI on VP2). We also want to be able to adjust the PLL output
> > > frequency on the fly to satisfy the requirements of the selected display
> > > mode.
> > > 
> > > And this is where I'm stuck. Trying to satisfy the requirements of up to
> > > three consumers while changing the PLL frequency on the fly sounds like
> > > a poorly tractable mathematical problem (is it 3-SAT?). We can take the
> > > HDMI output out of the equation, because it can be driven from the HDMI
> > > PHY (which is capable of arbitrary rates) instead of the mux, but that
> > > makes the decision of which dclk source to use for a VP block dependent on
> > > which downstream consumer is connected to it (HDMI vs. something else).
> > 
> > It becomes more messy: The HDMI PHY cannot be used as clock source
> > for modes exceeding 4K@60Hz.
> > 
> > > Even then we somehow need two devices to cooperate in picking a PLL
> > > frequency that satisfies the requirements of both of them, and change to it
> > > without display corruption. I'm not even sure if the CCF has mechanisms
> > > for that?..

It's not *just* the CCF though. You will disrupt the other, already
active display, which might affect the user because the screen will
blank, throw off the vblank timings and thus userspace, etc.

Brian's solution is great progress on that front already, but if you can
just save yourself the trouble, I'd advise you to do that instead :)

Maxime

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