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Thu, 23 Apr 2026 14:57:29 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 63NEvQO5011425; Thu, 23 Apr 2026 14:57:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4dm31k24b4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:26 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63NEvQnW011419; Thu, 23 Apr 2026 14:57:26 GMT Received: from hu-devc-hyd-u24-a.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.147.246.140]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 63NEvPrS011417 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:26 +0000 (GMT) Received: by hu-devc-hyd-u24-a.qualcomm.com (Postfix, from userid 429934) id E3BF521C47; Thu, 23 Apr 2026 20:27:24 +0530 (+0530) From: Mukesh Kumar Savaliya To: viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Mukesh Kumar Savaliya Subject: [PATCH v7 3/4] soc: qcom: geni-se: Keep pinctrl active for multi-owner controllers Date: Thu, 23 Apr 2026 20:25:50 +0530 Message-ID: <20260423145705.545552-4-mukesh.savaliya@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> References: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfX3wQntq8X80DI jdfK1b/mplihxHrqiHMq6M66n4l5ku3HLfiKXQCaiWNqCFmUKtkNuKR6oLOkZf7qUsNiBptMIrp UCxeDBsCZyab63xMxAlWJgzPU/EcwHtNUHdrCWyXIbQ6sdWuFfraAK/4aHwuPT2vLEskizDZEnq MprEdmwWjRW85/KT86bEyH7N9MI4Pb4f6AjDf0CXTtZw1c1xmU3XldMOs7ltQ8iXXvGBbkq7uHf GAY6oPRAt5Ztq4hJOVDyD+CMVAyh6422fIMI4fjoRofKJnlxTcu0WemV0RS0bPCQIK/DWw2UtUZ Vd6H64PHc8rxd027gknKFxbDRPXl/TD11M/hyOQqlTUKv5NEOqe2b5pmeyYNvC+QGav8dpF1QyG Ys98PQUgJYswh3wjCPoM8PHHrWiL27/Ls8k+1Oxf3abVaChe4aSelZSWPioZMOHUiEq1wV9yAtp ABLjXQ+MWblGP3YUmPQ== X-Authority-Analysis: v=2.4 cv=OeyoyBTY c=1 sm=1 tr=0 ts=69ea335a cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=AU6ItHRBSQEJJjuWNb0A:9 X-Proofpoint-GUID: yn-QgtGEoKNj2wWp8mn69598A6mtBZow X-Proofpoint-ORIG-GUID: yn-QgtGEoKNj2wWp8mn69598A6mtBZow X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230149 On platforms where a GENI Serial Engine is shared with another system processor, selecting the "sleep" pinctrl state can disrupt ongoing transfers initiated by the other processor. Teach geni_se_resources_off() to skip selecting the pinctrl sleep state when the Serial Engine is marked as shared, while still allowing the rest of the resource shutdown sequence to proceed. This is required for multi-owner configurations (described via DeviceTree with qcom,qup-multi-owner on the protocol controller node). Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Kumar Savaliya --- drivers/soc/qcom/qcom-geni-se.c | 15 +++++++++++---- include/linux/soc/qcom/geni-se.h | 2 ++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index cd1779b6a91a..1a60832ace16 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -597,10 +597,17 @@ int geni_se_resources_off(struct geni_se *se) if (has_acpi_companion(se->dev)) return 0; - - ret = pinctrl_pm_select_sleep_state(se->dev); - if (ret) - return ret; + /* + * Select the "sleep" pinctrl state only when the serial engine is + * exclusively owned by this system processor. For shared controller + * configurations, another system processor may still be using the pins, + * and switching them to "sleep" can disrupt ongoing transfers. + */ + if (!se->multi_owner) { + ret = pinctrl_pm_select_sleep_state(se->dev); + if (ret) + return ret; + } geni_se_clks_off(se); return 0; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 0a984e2579fe..46217cac73c3 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -63,6 +63,7 @@ struct geni_icc_path { * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE + * @multi_owner: True if SE is shared between multiple owners. */ struct geni_se { void __iomem *base; @@ -72,6 +73,7 @@ struct geni_se { unsigned int num_clk_levels; unsigned long *clk_perf_tbl; struct geni_icc_path icc_paths[3]; + bool multi_owner; }; /* Common SE registers */ -- 2.43.0