[PATCH 1/3] dt-bindings: PCI: altera: add binding for Agilex 5

[Mahesh Vaidya <mahesh.vaidya@altera.com>]

Add the compatible string for the Agilex 5 PCIe Hard IP root port
controller.

Co-developed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Co-developed-by: Peter Colberg <peter.colberg@intel.com>
Signed-off-by: Peter Colberg <peter.colberg@intel.com>
Signed-off-by: Mahesh Vaidya <mahesh.vaidya@altera.com>
---
 .../bindings/pci/altr,pcie-root-port.yaml     | 37 ++++++++++---------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
index f516db47ab20..f9c2089bad34 100644
--- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
+++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
@@ -8,16 +8,17 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: Altera PCIe Root Port
 
 maintainers:
-  - Matthew Gerlach <matthew.gerlach@linux.intel.com>
+  - Mahesh Vaidya <mahesh.vaidya@altera.com>
 
 properties:
   compatible:
     description: Each family of socfpga has its own implementation of the
       PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
       family of chips. The Stratix10 family of chips is supported by the
-      altr,pcie-root-port-2.0. The Agilex family of chips has three,
+      altr,pcie-root-port-2.0. The Agilex7 family of chips has three,
       non-register compatible, variants of PCIe Hard IP referred to as the
       F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
+      The altr,pcie-root-port-4.0 is used for the Agilex5 family of chips.
 
     enum:
       - altr,pcie-root-port-1.0
@@ -25,20 +26,15 @@ properties:
       - altr,pcie-root-port-3.0-f-tile
       - altr,pcie-root-port-3.0-p-tile
       - altr,pcie-root-port-3.0-r-tile
+      - altr,pcie-root-port-4.0
 
   reg:
-    items:
-      - description: TX slave port region
-      - description: Control register access region
-      - description: Hard IP region
     minItems: 2
+    maxItems: 3
 
   reg-names:
-    items:
-      - const: Txs
-      - const: Cra
-      - const: Hip
     minItems: 2
+    maxItems: 3
 
   interrupts:
     maxItems: 1
@@ -80,18 +76,25 @@ allOf:
     then:
       properties:
         reg:
-          maxItems: 2
-
+          items:
+            - description: TX slave port region
+            - description: Control register access region
         reg-names:
-          maxItems: 2
-
+          items:
+            - const: Txs
+            - const: Cra
     else:
       properties:
         reg:
-          minItems: 3
-
+          items:
+            - description: TX slave port region
+            - description: Control register access region
+            - description: Hard IP region
         reg-names:
-          minItems: 3
+          items:
+            - const: Txs
+            - const: Cra
+            - const: Hip
 
 unevaluatedProperties: false
 
-- 
2.34.1