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Fri, 24 Apr 2026 11:13:54 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v1 12/20] pinctrl: starfive: Add StarFive JHB100 per1 controller driver Date: Fri, 24 Apr 2026 04:13:22 -0700 Message-Id: <20260424111330.702272-13-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260424111330.702272-1-changhuang.liang@starfivetech.com> References: <20260424111330.702272-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0025.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::34) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1156:EE_ X-MS-Office365-Filtering-Correlation-Id: 7127f9db-57a4-4f51-d89a-08dea1f29276 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|376014|366016|1800799024|38350700014|921020|56012099003|18002099003|22082099003; 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Signed-off-by: Lianfeng Ouyang Signed-off-by: Changhuang Liang --- drivers/pinctrl/starfive/Kconfig | 12 ++ drivers/pinctrl/starfive/Makefile | 1 + .../starfive/pinctrl-starfive-jhb100-per1.c | 112 ++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c diff --git a/drivers/pinctrl/starfive/Kconfig b/drivers/pinctrl/starfive/Kconfig index e5afd937c4a1..c5937207b2d3 100644 --- a/drivers/pinctrl/starfive/Kconfig +++ b/drivers/pinctrl/starfive/Kconfig @@ -71,6 +71,18 @@ config PINCTRL_STARFIVE_JHB100_PER0 peripherals supporting inputs, outputs, configuring pull-up/pull-down and interrupts on input changes. +config PINCTRL_STARFIVE_JHB100_PER1 + tristate "StarFive JHB100 SoC Peripheral-1 pinctrl and GPIO driver" + depends on ARCH_STARFIVE || COMPILE_TEST + depends on OF + select PINCTRL_STARFIVE_JHB100 + default ARCH_STARFIVE + help + Say yes here to support Peripheral-1 pin control on the StarFive JHB100 SoC. + This also provides an interface to the GPIO pins not used by other + peripherals supporting inputs, outputs, configuring pull-up/pull-down + and interrupts on input changes. + config PINCTRL_STARFIVE_JHB100_SYS0 tristate "StarFive JHB100 SoC System-0 pinctrl and GPIO driver" depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/pinctrl/starfive/Makefile b/drivers/pinctrl/starfive/Makefile index f2bb0c35a2a0..6beef7e313ef 100644 --- a/drivers/pinctrl/starfive/Makefile +++ b/drivers/pinctrl/starfive/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_STARFIVE_JH7110_AON) += pinctrl-starfive-jh7110-aon.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100) += pinctrl-starfive-jhb100.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER0) += pinctrl-starfive-jhb100-per0.o +obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_PER1) += pinctrl-starfive-jhb100-per1.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0) += pinctrl-starfive-jhb100-sys0.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS0H) += pinctrl-starfive-jhb100-sys0h.o obj-$(CONFIG_PINCTRL_STARFIVE_JHB100_SYS1) += pinctrl-starfive-jhb100-sys1.o diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c new file mode 100644 index 000000000000..fcdc326ac50f --- /dev/null +++ b/drivers/pinctrl/starfive/pinctrl-starfive-jhb100-per1.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Pinctrl / GPIO driver for StarFive JHB100 SoC Peripheral-1 domain + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Alex Soo + * + */ + +#include +#include + +#include "pinctrl-starfive-jhb100.h" + +static const struct jhb100_pin_layout_desc jhb100_per1_pl_desc[] = { + { .pin_start = 0, .pin_cnt = 36, .name = "gpio", .gpio_func_sel = 0 }, + { 0xff }, +}; + +static struct config_reg_layout_desc jhb100_per1_pinctr_rldesc[] = { + { + .pin_start = 0, + .pin_cnt = 32, + .drive_strength_2bit = { .shift = 0, .width = 2 }, + .input_enable = { .shift = 2, .width = 1 }, + .pull_down = { .shift = 3, .width = 1 }, + .pull_up = { .shift = 4, .width = 1 }, + .slew_rate = { .shift = 5, .width = 1 }, + .schmitt_trigger_select = { .shift = 6, .width = 1 }, + .reserved = { .shift = 7, .width = 8 }, + .debounce_width = { .shift = 15, .width = 17 }, + }, + { + .pin_start = 32, + .pin_cnt = 4, + .input_enable = { .shift = 0, .width = 1 }, + .mode_select = { .shift = 1, .width = 2 }, + .pull_down = { .shift = 3, .width = 1 }, + .pull_up = { .shift = 4, .width = 1 }, + .open_drain_pull_up_sel = { .shift = 5, .width = 2 }, + .schmitt_trigger_select = { .shift = 7, .width = 1 }, + .reserved = { .shift = 8, .width = 7 }, + .debounce_width = { .shift = 15, .width = 17 }, + }, + { 0xff }, +}; + +static const struct pinvref_desc pinvref_desc_per0[] = { + { + .name = "gpioe-spi", + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + .name = "gpioe-qspi0", + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + .name = "gpioe-qspi1", + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { + .name = "gpioe-qspi2", + .range = BIT(JHB100_PINVREF_1_8V) | BIT(JHB100_PINVREF_3_3V) + }, + { NULL }, +}; + +struct starfive_pinctrl_regs jhb100_per1_pinctrl_regs = { + .vref = { .reg = 0x00, .pv_desc = pinvref_desc_per0 }, + .config = { .reg = 0x14, .width_per_pin = 32 }, + .output = { .reg = 0xa4, .width_per_pin = 1 }, + .output_en = { .reg = 0xac, .width_per_pin = 1 }, + .gpio_status = { .reg = 0xb4, .width_per_pin = 1 }, + .func_sel = { .reg = 0xbc, .width_per_pin = 2 }, + .irq_en = { .reg = 0xc8, .width_per_pin = 1 }, + .irq_status = { .reg = 0xd0, .width_per_pin = 1 }, + .irq_clr = { .reg = 0xd8, .width_per_pin = 1 }, + .irq_trigger = { .reg = 0xe0, .width_per_pin = 1 }, + .irq_level = { .reg = 0xe8, .width_per_pin = 1 }, + .irq_both_edge = { .reg = 0xf0, .width_per_pin = 1 }, + .irq_edge = { .reg = 0xf8, .width_per_pin = 1 }, +}; + +static const struct jhb100_pinctrl_domain_info jhb100_per1_pinctrl_info = { + .name = "jhb100-per1", + .gc_base = -1, + .pl_desc = jhb100_per1_pl_desc, + .crl_desc = jhb100_per1_pinctr_rldesc, + .regs = &jhb100_per1_pinctrl_regs, +}; + +static const struct of_device_id jhb100_per1_pinctrl_of_match[] = { + { + .compatible = "starfive,jhb100-per1-pinctrl", + .data = &jhb100_per1_pinctrl_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jhb100_per1_pinctrl_of_match); + +static struct platform_driver jhb100_per1_pinctrl_driver = { + .probe = jhb100_pinctrl_probe, + .driver = { + .name = "starfive-jhb100-per1-pinctrl", + .of_match_table = jhb100_per1_pinctrl_of_match, + }, +}; +module_platform_driver(jhb100_per1_pinctrl_driver); + +MODULE_DESCRIPTION("Pinctrl driver for StarFive JHB100 SoC Peripheral-1 domain"); +MODULE_AUTHOR("Alex Soo "); +MODULE_LICENSE("GPL"); -- 2.25.1