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Fri, 24 Apr 2026 11:14:05 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v1 20/20] riscv: dts: starfive: jhb100: Add pinctrl nodes Date: Fri, 24 Apr 2026 04:13:30 -0700 Message-Id: <20260424111330.702272-21-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260424111330.702272-1-changhuang.liang@starfivetech.com> References: <20260424111330.702272-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0025.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::34) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1156:EE_ X-MS-Office365-Filtering-Correlation-Id: 68261140-260c-4332-6554-08dea1f298f8 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|52116014|376014|366016|1800799024|38350700014|921020|56012099003|18002099003|22082099003; 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They contain pinctrl_per0/pinctrl_per1/pinctrl_per2/pinctrl_per2pok/pinctrl_per3/ pinctrl_sys0/pinctrl_sys0h/pinctrl_sys1/pinctrl_sys2. Signed-off-by: Lianfeng Ouyang Signed-off-by: Changhuang Liang --- .../boot/dts/starfive/jhb100-evb1-eth.dts | 27 +++++ arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi | 4 + .../boot/dts/starfive/jhb100-pinctrl.dtsi | 19 ++++ arch/riscv/boot/dts/starfive/jhb100.dtsi | 107 ++++++++++++++++++ 4 files changed, 157 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts index 62cd046e1224..f7e82f9d0ff1 100644 --- a/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1-eth.dts @@ -4,3 +4,30 @@ */ #include "jhb100-evb1.dtsi" + +&pinctrl_per0 { + gpioe-i3c0-vref = ; /* VREF for GPIOB8-11, 32-33 */ + gpioe-i3c1-vref = ; /* VREF for GPIOB12-15, 34-35 */ + gpioe-i3c2-vref = ; /* VREF for GPIOB16-23 */ + gpioe-i3c4-vref = ; /* VREF for GPIOB36-43 */ +}; + +&pinctrl_per1 { + gpioe-spi-vref = ; /* VREF for GPIOC0-4 */ + gpioe-qspi0-vref = ; /* VREF for GPIOC5-11 */ + gpioe-qspi1-vref = ; /* VREF for GPIOC12-19 */ + gpioe-qspi2-vref = ; /* VREF for GPIOC20-27 */ +}; + +&pinctrl_per2 { + gpionw-vref = ; /* VREF for GPIOD19-30 */ +}; + +&pinctrl_per3 { + gpios-vref = ; /* VREF for GPIOE0-10 */ +}; + +&pinctrl_sys2 { + gpiow-vref = ; /* VREF for GPIOA36-39 */ + gpiow-inner-vref = ; /* VREF for GPIOA40-43 */ +}; diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi index 462b6fb7953b..acd5949bcfdb 100644 --- a/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dtsi @@ -3,7 +3,9 @@ * Copyright (c) 2024-2026 StarFive Technology Co., Ltd. */ +#include "jhb100-pinfunc.h" #include "jhb100.dtsi" +#include "jhb100-pinctrl.dtsi" / { model = "StarFive JHB100 EVB-1"; @@ -29,4 +31,6 @@ memory@40000000 { &uart6 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_pins>; }; diff --git a/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi new file mode 100644 index 000000000000..d12b79376521 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jhb100-pinctrl.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2025-2026 StarFive Technology Co., Ltd. + */ + +&pinctrl_sys2 { + uart6_pins: uart6-grp { + uart6-tx-pins { + pinmux = ; + }; + + uart6-rx-pins { + pinmux = ; + input-enable; + }; + }; +}; diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi index 700d00f800bc..74d427d7f2df 100644 --- a/arch/riscv/boot/dts/starfive/jhb100.dtsi +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi @@ -425,6 +425,18 @@ per0crg: clock-controller@11a08000 { #reset-cells = <1>; }; + pinctrl_per0: pinctrl@11a0a000 { + compatible = "starfive,jhb100-per0-pinctrl"; + reg = <0x0 0x11a0a000 0x0 0x1000>; + resets = <&per0crg JHB100_PER0RST_GPIO_IOMUX_PRESETN>; + interrupts = <60>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per0 0 0 60>; + }; + per1crg: clock-controller@11b40000 { compatible = "starfive,jhb100-per1crg"; reg = <0x0 0x11b40000 0x0 0x1000>; @@ -440,6 +452,18 @@ per1crg: clock-controller@11b40000 { #reset-cells = <1>; }; + pinctrl_per1: pinctrl@11b42000 { + compatible = "starfive,jhb100-per1-pinctrl"; + reg = <0x0 0x11b42000 0x0 0x800>; + resets = <&per1crg JHB100_PER1RST_IOMUX_PRESETN>; + interrupts = <61>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per1 0 0 36>; + }; + per2crg: clock-controller@11bc0000 { compatible = "starfive,jhb100-per2crg"; reg = <0x0 0x11bc0000 0x0 0x1000>; @@ -461,6 +485,30 @@ per2crg: clock-controller@11bc0000 { #reset-cells = <1>; }; + pinctrl_per2: pinctrl@11bc2000 { + compatible = "starfive,jhb100-per2-pinctrl"; + reg = <0x0 0x11bc2000 0x0 0x400>; + resets = <&per2crg JHB100_PER2RST_IOMUX_PRESETN>; + interrupts = <62>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per2 0 0 31>; + }; + + pinctrl_per2pok: pinctrl@11bc2400 { + compatible = "starfive,jhb100-per2pok-pinctrl"; + reg = <0x0 0x11bc2400 0x0 0x400>; + resets = <&per2crg JHB100_PER2RST_POK_IOMUX_PRESETN>; + interrupts = <63>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per2pok 0 0 18>; + }; + per3crg: clock-controller@11c40000 { compatible = "starfive,jhb100-per3crg"; reg = <0x0 0x11c40000 0x0 0x1000>; @@ -480,6 +528,18 @@ per3crg: clock-controller@11c40000 { #reset-cells = <1>; }; + pinctrl_per3: pinctrl@11c42000 { + compatible = "starfive,jhb100-per3-pinctrl"; + reg = <0x0 0x11c42000 0x0 0x1000>; + resets = <&per3crg JHB100_PER3RST_IOMUX_PRESETN>; + interrupts = <64>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_per3 0 0 11>; + }; + sys0crg: clock-controller@13000000 { compatible = "starfive,jhb100-sys0crg"; reg = <0x0 0x13000000 0x0 0x4000>; @@ -513,6 +573,53 @@ sys2crg: clock-controller@13008000 { #clock-cells = <1>; #reset-cells = <1>; }; + + pinctrl_sys0: pinctrl@13080000 { + compatible = "starfive,jhb100-sys0-pinctrl"; + reg = <0x0 0x13080000 0x0 0x800>; + resets = <&sys0crg JHB100_SYS0RST_SYS0_IOMUX_PRESETN>; + interrupts = <56>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys0 0 0 4>; + }; + + pinctrl_sys0h: pinctrl@13080800 { + compatible = "starfive,jhb100-sys0h-pinctrl"; + reg = <0x0 0x13080800 0x0 0x800>; + resets = <&sys0crg JHB100_SYS0RST_SYS0H_IOMUX_PRESETN>; + interrupts = <57>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys0h 0 0 12>; + }; + + pinctrl_sys1: pinctrl@13081000 { + compatible = "starfive,jhb100-sys1-pinctrl"; + reg = <0x0 0x13081000 0x0 0x1000>; + resets = <&sys1crg JHB100_SYS1RST_SYS1_IOMUX_PRESETN>; + interrupts = <58>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys1 0 0 8>; + }; + + pinctrl_sys2: pinctrl@13082000 { + compatible = "starfive,jhb100-sys2-pinctrl"; + reg = <0x0 0x13082000 0x0 0x1000>; + interrupts = <59>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sys2 0 0 37>; + }; }; }; }; -- 2.25.1