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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12dca2c1c16sm11449051c88.5.2026.04.26.17.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 17:52:49 -0700 (PDT) From: Shawn Guo To: Jassi Brar Cc: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH v2 0/2] Add CPUCP mailbox support for Qualcomm Nord SoC Date: Mon, 27 Apr 2026 08:52:34 +0800 Message-ID: <20260427005236.230106-1-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDAwNiBTYWx0ZWRfX3c8AufrzjQIn bbQgfMwqn0uD+mD4C5q+TiYOlJAH0uu22AuyPBULybdxfaPcoWqt9c2ZasxGU3W+V0UwAV4hSLW 1EoQ7JpLKPdDH8PYLTo/ui3qGN8b+XBtq7Qpnzq+jh7Q984DBkFEHeAKGLZZyKafUI+NjaCd8Qk QOijhB1BEnXSjNmtM5EgYzajUK+kDv68GGPtHFHou/16HDA0W50VjmRXYOfaMG3in0pjg1HJLx1 /4F5fyLsoPUnm7rwZIayee8ypGySozKHPf8YqtQJZqP+DOk4QpEdfwb/oWZX+yRnhrvsgDPusxS VM+FrU+jw7YO4K1GmhhbhcJS6jHs9hwJzADVtgPJ88ZhgK0u2APYxhx0gSfIvA4kZyeb8DMB+fo i2qXhD2DTMlLklGt2/eyLeAw9UFfHGeC2hpFUMm1z1FQAeequQB30tLbT3c2TEwH6fT/VSJ8Vnf 7kZarFOfXKM6MUsr1qA== X-Proofpoint-ORIG-GUID: __x-I7qEc-Eh7V3wHzmW3WGiz6DblioU X-Authority-Analysis: v=2.4 cv=RaGgzVtv c=1 sm=1 tr=0 ts=69eeb363 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=wFnvaYuheMr2fJ8iLyYA:9 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-GUID: __x-I7qEc-Eh7V3wHzmW3WGiz6DblioU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_07,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 spamscore=0 clxscore=1015 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270006 This series adds CPUCP mailbox controller support for Qualcomm Nord SoC. The Nord CPUCP mailbox is functionally identical to the existing x1e80100 implementation, except it exposes 16 IPC channels instead of 3. Patch 1 adds the Nord compatible string to the DT binding. Patch 2 refactors the channel count from a hardcoded compile-time constant into a per-hardware configuration struct populated via the device tree match data Changes in v2: - List Nord CPUCP as compatible with X1E80100 CPUCP in binding - Drop the unnecessary change on @chans comment from the driver patch - Link to v1: https://lore.kernel.org/all/20260420034932.1247344-1-shengchao.guo@oss.qualcomm.com/ Deepti Jaggi (2): dt-bindings: mailbox: qcom: Document Nord CPUCP mailbox controller mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller .../bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + drivers/mailbox/qcom-cpucp-mbox.c | 35 ++++++++++++++++--- 2 files changed, 31 insertions(+), 5 deletions(-) -- 2.43.0