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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12dca2c1c16sm11449051c88.5.2026.04.26.17.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 17:52:58 -0700 (PDT) From: Shawn Guo To: Jassi Brar Cc: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH v2 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller Date: Mon, 27 Apr 2026 08:52:36 +0800 Message-ID: <20260427005236.230106-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427005236.230106-1-shengchao.guo@oss.qualcomm.com> References: <20260427005236.230106-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=K8QS2SWI c=1 sm=1 tr=0 ts=69eeb385 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=OYxAFmqQ0AEWrUtYbScA:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-ORIG-GUID: E_8k85OfuSjfSBzVmqYOt2ydO2JfkiWK X-Proofpoint-GUID: E_8k85OfuSjfSBzVmqYOt2ydO2JfkiWK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDAwNiBTYWx0ZWRfXzeA3EJaEaBh0 OVRbEUV+fn8jOAw7iEnS+kDpudiUXr71ClCrQedTG23EGkfid0ASophfD5g28Tp9QkMjYUyvQoX Mgaz7Fvo6RhYrtfolXHmXioCzl/TS86Qaxx/IBR78BdsPVL1D6Mri3Z0snn3Me50whOz6HNFsU2 8sAwVYgavdTCxVxOqeXGv65UInp3ew4tkPW7GpwUu7OPBK1nl2cFrL7x/HGFxEOX2CJcP+bFMgb l7h24kWqzfLZgrF9x+XX1KPIDE1UwIc7DJ/E0wXppZGDysPX//aArwW59JqmRoJrHpbIwc7bFfU nQySvoOeQOoCW9RECCfELffw0DRbt62HhoYB7TeUqyzykbHVJp2OdLUAQJQDTdVNk0oj/+hbvHH UU/yenOTVFNrVdBM2IwDrtxoaqo0zw1RWkzHv9Sku/dL6a65bzeJOjJTqGVqfwdPJo7VBQv5bmq U6jCL//gPCcJFodblxA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_07,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 phishscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270006 From: Deepti Jaggi The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on x1e80100. The existing driver hardcodes the channel count via a compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it impossible to support hardware with a different number of channels. Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that carries the channel count, and retrieve it via of_device_get_match_data() at probe time. Switch the channel array from a fixed-size member to a dynamically allocated buffer sized from the hardware data. Update the x1e80100 entry to supply its own data struct, and add a new Nord entry with num_chans = 16. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo --- drivers/mailbox/qcom-cpucp-mbox.c | 35 ++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c index 44f4ed15f818..862e45e8fbd5 100644 --- a/drivers/mailbox/qcom-cpucp-mbox.c +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -12,7 +12,6 @@ #include #include -#define APSS_CPUCP_IPC_CHAN_SUPPORTED 3 #define APSS_CPUCP_MBOX_CMD_OFF 0x4 /* Tx Registers */ @@ -26,6 +25,14 @@ #define APSS_CPUCP_RX_MBOX_EN 0x4c00 #define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0) +/** + * struct qcom_cpucp_mbox_data - Per-hardware mailbox configuration data + * @num_chans: Number of IPC channels supported by this hardware + */ +struct qcom_cpucp_mbox_data { + int num_chans; +}; + /** * struct qcom_cpucp_mbox - Holder for the mailbox driver * @chans: The mailbox channel @@ -34,7 +41,7 @@ * @rx_base: Base address of the CPUCP rx registers */ struct qcom_cpucp_mbox { - struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED]; + struct mbox_chan *chans; struct mbox_controller mbox; void __iomem *tx_base; void __iomem *rx_base; @@ -53,7 +60,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); - for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORTED) { + for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); struct mbox_chan *chan = &cpucp->chans[i]; unsigned long flags; @@ -112,15 +119,24 @@ static const struct mbox_chan_ops qcom_cpucp_mbox_chan_ops = { static int qcom_cpucp_mbox_probe(struct platform_device *pdev) { + const struct qcom_cpucp_mbox_data *data; struct device *dev = &pdev->dev; struct qcom_cpucp_mbox *cpucp; struct mbox_controller *mbox; int irq, ret; + data = of_device_get_match_data(dev); + if (!data) + return dev_err_probe(dev, -EINVAL, "No match data found\n"); + cpucp = devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL); if (!cpucp) return -ENOMEM; + cpucp->chans = devm_kcalloc(dev, data->num_chans, sizeof(*cpucp->chans), GFP_KERNEL); + if (!cpucp->chans) + return -ENOMEM; + cpucp->rx_base = devm_of_iomap(dev, dev->of_node, 0, NULL); if (IS_ERR(cpucp->rx_base)) return PTR_ERR(cpucp->rx_base); @@ -146,7 +162,7 @@ static int qcom_cpucp_mbox_probe(struct platform_device *pdev) mbox = &cpucp->mbox; mbox->dev = dev; - mbox->num_chans = APSS_CPUCP_IPC_CHAN_SUPPORTED; + mbox->num_chans = data->num_chans; mbox->chans = cpucp->chans; mbox->ops = &qcom_cpucp_mbox_chan_ops; @@ -157,8 +173,17 @@ static int qcom_cpucp_mbox_probe(struct platform_device *pdev) return 0; } +static const struct qcom_cpucp_mbox_data qcom_x1e80100_mbox_data = { + .num_chans = 3, +}; + +static const struct qcom_cpucp_mbox_data qcom_nord_mbox_data = { + .num_chans = 16, +}; + static const struct of_device_id qcom_cpucp_mbox_of_match[] = { - { .compatible = "qcom,x1e80100-cpucp-mbox" }, + { .compatible = "qcom,nord-cpucp-mbox", .data = &qcom_nord_mbox_data }, + { .compatible = "qcom,x1e80100-cpucp-mbox", .data = &qcom_x1e80100_mbox_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpucp_mbox_of_match); -- 2.43.0