From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>,
Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Shawn Guo <shengchao.guo@oss.qualcomm.com>
Subject: [PATCH 0/4] Add initial device trees for Nord SA8797P
Date: Mon, 27 Apr 2026 10:34:51 +0800 [thread overview]
Message-ID: <20260427023455.236410-1-shengchao.guo@oss.qualcomm.com> (raw)
This series adds initial device tree support for Qualcomm's Nord SA8797P
SoC and the SA8797P Ride reference board.
The Nord is a new generation of SoC series from Qualcomm built around
18 Oryon cores (qcom,oryon-1-5) organized in three clusters. SA8797P
is the automotive variant in the family. The IoT variant IQ-10 will be
added later, by sharing the base nord.dtsi with SA8797P.
The series is organized as follows:
- Patch 1/4 adds nord.dtsi, the base device tree for the Nord SoC series,
covering CPU topology with PSCI-based power management and idle states,
GICv3 interrupt controller with ITS, TLMM GPIO/pinctrl, 8 TSENS thermal
sensors, 3 APPS SMMU-500 instances, 3 QUPv3 GENI SE QUP blocks, PDP
SCMI channel and mailbox, watchdog, TRNG, TCSR, CMD-DB, firmware SCM,
reserved memory, PSCI and architected timers.
- Patch 2/4 adds nord-sa8797p.dtsi, the SA8797P SoC-level include on top
of nord.dtsi. It reserves 64 SCMI shared memory regions for SMC-based
firmware communication, enables three QUPv3 UART controllers with SCMI
power and performance domains, the UFS host controller and GPU SMMU with
their respective SCMI power domains. A new scmi-common.dtsi is also
introduced to factor out the firmware-level SCMI channel nodes shared
across SCMI-based SoCs.
- Patch 3/4 documents the SA8797P Ride board compatible string in the
dt-bindings.
- Patch 4/4 adds sa8797p-ride.dts, the board-level device tree for the
SA8797P Ride reference board, enabling UART15 as the primary console,
UART4 as secondary serial, UFS storage, and thermal zones for PMIC dies,
UFS and two SDRAM sensors via the SCMI sensor protocol on channel 23.
The dependent driver/binding changes:
- SoC ID: https://lore.kernel.org/all/20260427003531.229671-1-shengchao.guo@oss.qualcomm.com/
- CPUs: https://lore.kernel.org/all/20260427004619.229843-1-shengchao.guo@oss.qualcomm.com/
- CPUCP mailbox: https://lore.kernel.org/all/20260427005236.230106-1-shengchao.guo@oss.qualcomm.com/
- GENI SE QUP: https://lore.kernel.org/all/20260427005901.230237-1-shengchao.guo@oss.qualcomm.com/
- Serial: https://lore.kernel.org/all/20260427010114.230341-1-shengchao.guo@oss.qualcomm.com/
- ICE: https://lore.kernel.org/all/20260427010527.230473-1-shengchao.guo@oss.qualcomm.com/
- Interconnect: https://lore.kernel.org/all/20260420021351.1239355-1-shengchao.guo@oss.qualcomm.com/
- PDC: https://lore.kernel.org/all/20260427010922.230586-1-shengchao.guo@oss.qualcomm.com/
- PMIC PMAU0102 model: https://lore.kernel.org/all/20260419131523.1232835-1-shengchao.guo@oss.qualcomm.com/
- RPMH regulator: https://lore.kernel.org/all/20260427011159.230698-1-shengchao.guo@oss.qualcomm.com/
- RPMH powerdomain: https://lore.kernel.org/all/20260414035909.652992-1-shengchao.guo@oss.qualcomm.com/
- SCM: https://lore.kernel.org/all/20260427011346.230844-1-shengchao.guo@oss.qualcomm.com/
- APPS SMMU: https://lore.kernel.org/all/20260427011728.231026-1-shengchao.guo@oss.qualcomm.com/
- TCSR: https://lore.kernel.org/all/20260427012116.231226-1-shengchao.guo@oss.qualcomm.com/
- TLMM: https://lore.kernel.org/all/20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com/
- TRNG: https://lore.kernel.org/all/20260427012308.231350-1-shengchao.guo@oss.qualcomm.com/
- TSENS: https://lore.kernel.org/all/20260427012511.231475-1-shengchao.guo@oss.qualcomm.com/
- UFS PHY: https://lore.kernel.org/all/20260427012732.231611-1-shengchao.guo@oss.qualcomm.com/
- UFS: https://lore.kernel.org/all/20260427013115.231731-1-shengchao.guo@oss.qualcomm.com/
- Watchdog: https://lore.kernel.org/all/20260427013236.231841-1-shengchao.guo@oss.qualcomm.com/
Deepti Jaggi (2):
arm64: dts: qcom: Add device tree for Nord SA8797P SoC
arm64: dts: qcom: Add device tree for SA8797P Ride board
Shawn Guo (2):
arm64: dts: qcom: Add device tree for Nord SoC series
dt-bindings: arm: qcom: Document SA8797P Ride board
.../devicetree/bindings/arm/qcom.yaml | 6 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/nord-sa8797p.dtsi | 941 ++++
arch/arm64/boot/dts/qcom/nord.dtsi | 4511 +++++++++++++++++
arch/arm64/boot/dts/qcom/sa8797p-ride.dts | 306 ++
arch/arm64/boot/dts/qcom/scmi-common.dtsi | 1918 +++++++
6 files changed, 7683 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/nord-sa8797p.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/nord.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/sa8797p-ride.dts
create mode 100644 arch/arm64/boot/dts/qcom/scmi-common.dtsi
--
2.43.0
next reply other threads:[~2026-04-27 2:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-27 2:34 Shawn Guo [this message]
2026-04-27 2:34 ` [PATCH 1/4] arm64: dts: qcom: Add device tree for Nord SoC series Shawn Guo
2026-04-28 7:24 ` Krzysztof Kozlowski
2026-04-28 7:28 ` Krzysztof Kozlowski
2026-04-28 13:09 ` Shawn Guo
2026-04-27 2:34 ` [PATCH 2/4] arm64: dts: qcom: Add device tree for Nord SA8797P SoC Shawn Guo
2026-04-27 2:34 ` [PATCH 3/4] dt-bindings: arm: qcom: Document SA8797P Ride board Shawn Guo
2026-04-28 7:23 ` Krzysztof Kozlowski
2026-04-28 13:03 ` Shawn Guo
2026-04-27 2:34 ` [PATCH 4/4] arm64: dts: qcom: Add device tree for " Shawn Guo
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