[PATCH 1/2] dt-bindings: interconnect: document the RPM Network-On-Chip interconnect in Shikra SoC

Raviteja Laggyshetty
2026-04-29T14:04:06Z

Document the RPM Network-On-Chip Interconnect for the Qualcomm
Shikra platform.

Co-developed-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Odelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
---
.../bindings/interconnect/qcom,shikra.yaml | 135 +++++++++++++++++++++
include/dt-bindings/interconnect/qcom,shikra.h | 121 ++++++++++++++++++
2 files changed, 256 insertions(+)

diff --git a/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml
new file mode 100644
index 000000000000..945bbeeb00ca
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,shikra.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Shikra Network-On-Chip interconnect
+
+maintainers:
+ - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
+
+description: |
+ The Qualcomm Shikra interconnect providers support adjusting the
+ bandwidth requirements between the various NoC fabrics.
+
+properties:
+ compatible:
+ enum:
+ - qcom,shikra-config-noc
+ - qcom,shikra-mem-noc-core
+ - qcom,shikra-sys-noc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+# Child node's properties
+patternProperties:
+ '^interconnect-[a-z0-9]+$':
+ type: object
+ description:
+ The interconnect providers do not have a separate QoS register space,
+ but share parent's space.
+
+ $ref: qcom,rpm-common.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,shikra-clk-virt
+ - qcom,shikra-mc-virt
+ - qcom,shikra-mmrt-virt
+ - qcom,shikra-mmnrt-virt
+
+ required:
+ - compatible
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+
+allOf:
+ - $ref: qcom,rpm-common.yaml#
+ - if:
+ properties:
+ compatible:
+ const: qcom,shikra-mem-noc-core
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: GPU-NoC AXI clock
+
+ clock-names:
+ items:
+ - const: gpu_axi
+
+ - if:
+ properties:
+ compatible:
+ const: qcom,shikra-sys-noc
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: EMAC0-NoC AXI clock.
+ - description: EMAC1-NoC AXI clock.
+ - description: USB2-NoC AXI clock.
+ - description: USB3-NoC AXI clock.
+
+ clock-names:
+ items:
+ - const: emac0_axi
+ - const: emac1_axi
+ - const: usb2_axi
+ - const: usb3_axi
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - qcom,shikra-clk-virt
+ - qcom,shikra-config-noc
+ - qcom,shikra-mc-virt
+ - qcom,shikra-mmrt-virt
+ - qcom,shikra-mmnrt-virt
+
+ then:
+ properties:
+ clocks: false
+ clock-names: false
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ snoc: interconnect@1880000 {
+ compatible = "qcom,shikra-sys-noc";
+ reg = <0x01880000 0x6a080>;
+ #interconnect-cells = <2>;
+ clocks = <&gcc_emac0_axi_sys_noc_clk>,
+ <&gcc_emac1_axi_sys_noc_clk>,
+ <&gcc_sys_noc_usb2_prim_axi_clk>,
+ <&gcc_sys_noc_usb3_prim_axi_clk>;
+ clock-names = "emac0_axi",
+ "emac1_axi",
+ "usb2_axi",
+ "usb3_axi";
+
+ clk_virt: interconnect-clk {
+ compatible = "qcom,shikra-clk-virt";
+ #interconnect-cells = <2>;
+ };
+ };
diff --git a/include/dt-bindings/interconnect/qcom,shikra.h b/include/dt-bindings/interconnect/qcom,shikra.h
new file mode 100644
index 000000000000..a42ea22ee162
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,shikra.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SHIKRA_H
+
+#define MASTER_QUP_CORE_0 0
+#define SLAVE_QUP_CORE_0 1
+
+#define SNOC_CNOC_MAS 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_AHB2PHY_USB 2
+#define SLAVE_APSS_THROTTLE_CFG 3
+#define SLAVE_AUDIO 4
+#define SLAVE_BOOT_ROM 5
+#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6
+#define SLAVE_CAMERA_CFG 7
+#define SLAVE_CDSP_THROTTLE_CFG 8
+#define SLAVE_CLK_CTL 9
+#define SLAVE_DSP_CFG 10
+#define SLAVE_RBCPR_CX_CFG 11
+#define SLAVE_RBCPR_MX_CFG 12
+#define SLAVE_CRYPTO_0_CFG 13
+#define SLAVE_DDR_SS_CFG 14
+#define SLAVE_DISPLAY_CFG 15
+#define SLAVE_EMAC0_CFG 16
+#define SLAVE_EMAC1_CFG 17
+#define SLAVE_GPU_CFG 18
+#define SLAVE_GPU_THROTTLE_CFG 19
+#define SLAVE_HWKM 20
+#define SLAVE_IMEM_CFG 21
+#define SLAVE_MAPSS 22
+#define SLAVE_MDSP_MPU_CFG 23
+#define SLAVE_MESSAGE_RAM 24
+#define SLAVE_MSS 25
+#define SLAVE_PCIE_CFG 26
+#define SLAVE_PDM 27
+#define SLAVE_PIMEM_CFG 28
+#define SLAVE_PKA_WRAPPER_CFG 29
+#define SLAVE_PMIC_ARB 30
+#define SLAVE_QDSS_CFG 31
+#define SLAVE_QM_CFG 32
+#define SLAVE_QM_MPU_CFG 33
+#define SLAVE_QPIC 34
+#define SLAVE_QUP_0 35
+#define SLAVE_RPM 36
+#define SLAVE_SDCC_1 37
+#define SLAVE_SDCC_2 38
+#define SLAVE_SECURITY 39
+#define SLAVE_SNOC_CFG 40
+#define SNOC_SF_THROTTLE_CFG 41
+#define SLAVE_TLMM 42
+#define SLAVE_TSCSS 43
+#define SLAVE_USB2 44
+#define SLAVE_USB3 45
+#define SLAVE_VENUS_CFG 46
+#define SLAVE_VENUS_THROTTLE_CFG 47
+#define SLAVE_VSENSE_CTRL_CFG 48
+#define SLAVE_SERVICE_CNOC 49
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI_CH0 1
+
+#define MASTER_GRAPHICS_3D 0
+#define MASTER_MNOC_HF_MEM_NOC 1
+#define MASTER_ANOC_PCIE_MEM_NOC 2
+#define MASTER_SNOC_SF_MEM_NOC 3
+#define MASTER_AMPSS_M0 4
+#define MASTER_SYS_TCU 5
+#define SLAVE_LLCC 6
+#define SLAVE_MEMNOC_SNOC 7
+#define SLAVE_MEM_NOC_PCIE_SNOC 8
+
+#define MASTER_CAMNOC_SF 0
+#define MASTER_VIDEO_P0 1
+#define MASTER_VIDEO_PROC 2
+#define SLAVE_MMNRT_VIRT 3
+
+#define MASTER_CAMNOC_HF 0
+#define MASTER_MDP_PORT0 1
+#define MASTER_MMRT_VIRT 2
+#define SLAVE_MM_MEMNOC 3
+
+#define MASTER_SNOC_CFG 0
+#define MASTER_TIC 1
+#define MASTER_ANOC_SNOC 2
+#define MASTER_MEMNOC_PCIE 3
+#define MASTER_MEMNOC_SNOC 4
+#define MASTER_PIMEM 5
+#define MASTER_PCIE2_0 6
+#define MASTER_QDSS_BAM 7
+#define MASTER_QPIC 8
+#define MASTER_QUP_0 9
+#define CNOC_SNOC_MAS 10
+#define MASTER_AUDIO 11
+#define MASTER_EMAC_0 12
+#define MASTER_EMAC_1 13
+#define MASTER_QDSS_ETR 14
+#define MASTER_SDCC_1 15
+#define MASTER_SDCC_2 16
+#define MASTER_USB2_0 17
+#define MASTER_USB3 18
+#define MASTER_CRYPTO_CORE0 19
+#define SLAVE_APPSS 20
+#define SLAVE_MCUSS 21
+#define SLAVE_WCSS 22
+#define SLAVE_MEMNOC_SF 23
+#define SNOC_CNOC_SLV 24
+#define SLAVE_BOOTIMEM 25
+#define SLAVE_OCIMEM 26
+#define SLAVE_PIMEM 27
+#define SLAVE_SERVICE_SNOC 28
+#define SLAVE_PCIE2_0 29
+#define SLAVE_QDSS_STM 30
+#define SLAVE_TCU 31
+#define SLAVE_PCIE_MEMNOC 32
+#define SLAVE_ANOC_SNOC 33
+
+#endif

--
2.43.0