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([121.160.151.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed5f30ddsm502899b3a.26.2026.04.28.20.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 20:51:39 -0700 (PDT) From: Chanhong Jung To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: gpio: fairchild,74hc595: add lines-initial-states property Date: Wed, 29 Apr 2026 12:51:33 +0900 Message-Id: <20260429035134.1023330-2-happycpu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The 74HC595 and 74LVC594 shift registers latch their outputs until the first serial write, so boards that depend on a specific power-on pattern (for example active-low indicators, reset lines, or other signals that must come up non-zero) have no way to express that today: the Linux driver always writes zeros from its zero-initialised buffer during probe. Document support for the existing lines-initial-states bitmask, already defined for nxp,pcf8575, so the same convention covers this output-only device. Bit N corresponds to GPIO line N. Because the 74HC595/74LVC594 family is push-pull output only (no input mode, no high-impedance state under software control), bit=0 drives the line low and bit=1 drives it high; this differs from nxp,pcf8575, where the 0/1 polarity reflects the quasi-bidirectional nature of that part. The bitmask covers up to 32 lines, which fits the typical 1-4 chip cascades that appear in tree. Should longer chains require seeding in the future, the property can be extended to a uint32-array without breaking the bit-N-equals-line-N convention. Suggested-by: Linus Walleij Signed-off-by: Chanhong Jung --- .../devicetree/bindings/gpio/fairchild,74hc595.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 23410aeca..451538df6 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -45,6 +45,18 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of daisy-chained shift registers + lines-initial-states: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask that specifies the initial state of each output line, written + by the driver before the gpiochip is registered. Bit N corresponds to + GPIO line N, following the convention already documented for + nxp,pcf8575. Because the 74HC595/74LVC594 family is push-pull output + only, a bit set to zero drives the line low and a bit set to one + drives it high. The bitmask covers up to 32 lines (four cascaded + registers); outputs beyond that come up zeroed. When the property is + absent all outputs come up low, preserving the previous behaviour. + enable-gpios: description: GPIO connected to the OE (Output Enable) pin. maxItems: 1 @@ -79,6 +91,7 @@ examples: gpio-controller; #gpio-cells = <2>; registers-number = <4>; + lines-initial-states = <0xffff0000>; spi-max-frequency = <100000>; }; }; -- 2.34.1