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Date: Mon, 4 May 2026 11:54:11 +0200
From: Krzysztof Kozlowski <krzk@kernel.org>
To: Inochi Amaoto <inochiama@gmail.com>
Cc: Vinod Koul <vkoul@kernel.org>, 
	Neil Armstrong <neil.armstrong@linaro.org>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>, 
	Kees Cook <kees@kernel.org>, "Gustavo A. R. Silva" <gustavoars@kernel.org>, 
	Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alex@ghiti.fr>, Ze Huang <huang.ze@linux.dev>, 
	Alex Elder <elder@riscstar.com>, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, 
	linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, 
	linux-hardening@vger.kernel.org, Yixun Lan <dlan@gentoo.org>, Longbin Li <looong.bin@gmail.com>
Subject: Re: [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy
 support
Message-ID: <20260504-logical-nice-python-1e1f43@quoll>
References: <20260430022843.1090138-1-inochiama@gmail.com>
 <20260430022843.1090138-2-inochiama@gmail.com>
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In-Reply-To: <20260430022843.1090138-2-inochiama@gmail.com>

On Thu, Apr 30, 2026 at 10:28:40AM +0800, Inochi Amaoto wrote:
> +properties:
> +  compatible:
> +    const: spacemit,k3-comb-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  "#phy-cells":
> +    const: 2
> +    description:
> +      The first one is phy id, the second one is phy type.

You could mention here the defines representing supported phy types.

> +
> +  spacemit,apb-spare:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to APB SPARE system controller interface, used for
> +      PHY calibration.
> +
> +  spacemit,apmu:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      - items:
> +          - description: phandle of APMU syscon
> +          - description: configuration of the PHY lanes
> +    description: |
> +      Phandle to control PHY mux configuration. The configuration
> +      is described as follows:
> +      bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode
> +      bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode
> +      bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode
> +      bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode
> +      bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode

I assume this device k3-comb-phy handles phys for PCIe A, B, C and D?

> +
> +      The bit[3:0] is only valid when bit 4 is 1.
> +
> +required:
> +  - compatible

reg required.

> +  - "#phy-cells"
> +  - spacemit,apb-spare
> +  - spacemit,apmu
> +
> +additionalProperties: false

Best regards,
Krzysztof