From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE750406297 for ; Tue, 5 May 2026 07:01:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777964516; cv=none; b=qZpTeXOWXuiNOQZIB0Z4uBlCrqynGJdRJRofVSXzPnEk5w/kAbcYTI3A137gKiErjdOYpaBMOSStpeBbIO6E50EG/drlGzxQgVGVZuSOhRx3eyqH8VwXUyRPZo8VqTWiQYd6UFkJ5DPDv5RmwteC1ZjEH6ozKNMkx5ewsVpDb/8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777964516; c=relaxed/simple; bh=GxPcM3D6fcOBB3Z1Td+dY6rhZmNKqLALfdcwQqF+Y6E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dfvh2EDrOOMVhl9tk/vBUSMsTnbtbutdmFju3CUIrLz2cYwF7b1zy0Tm1VzOq+5xYrpKbWIDBpqjNS3RvWSZW4rZsusysgNWTmxX0IBe7jRxkzTqj8/KlT5+/qQ5Bxb7i8jjaOxjxTJzPaR4QUMO8skbfMzzs1k/e63VRzzKknI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=c6EjMZj1; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JxLLNKHL; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="c6EjMZj1"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JxLLNKHL" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6456lieW3187556 for ; Tue, 5 May 2026 07:01:54 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ncTxOLmgEHRNxr9Ra/M7hKec3vLSGGKsocfqCJZ4FKQ=; b=c6EjMZj11urnTpN+ gJnvzh5d2UxNaM+w0CpimIzwFMWIJelcW5WfAtOCRCnqcAwTM+DZ4mMIsgoueTFh jOYkoP11Chbvc/yOo71diE9FaLR87vwvGEFRNEMIpKerAi8B8N4z3qtsk0Mk4kgR Ua7hRnalaqxzTCHZSGut1FyVyEawrBZ8GV+TQZX+DMAp0gmPRjXEms6wHr5Y0qXY FBUTeFoXaopJx/vlBWu4SKJAt4YIBdi6wuKvk1JTI+SZLD1usn3AdgzU2TjoaD+Y I7rlDKcxrLqcPqvkzE24e82NJclVZLHx48YL9+2NDB5uflrjuXuQhzYfEI5hStd0 XayzwQ== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dybkk81et-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 05 May 2026 07:01:53 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-3653638874cso2334909a91.2 for ; Tue, 05 May 2026 00:01:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777964513; x=1778569313; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ncTxOLmgEHRNxr9Ra/M7hKec3vLSGGKsocfqCJZ4FKQ=; b=JxLLNKHLNwC5a7zQ8A0YqZ/UVDbc9KcqFrRBjeDIBvEHasbjeE2ESUQ2pzt5G69Myb 54MQt5fkhi+SGH1jgQJKZmu+NsXcw/oDv0Xp9vqBrqcmRwquffII3KPsHC/OYvmboCa3 EmG3yyKNBepoWr3MvcasMrKAOivFC7x0ka3m/Bk3KxxJ+Apu6lUvvsOp8ec2hJ0xW2bt VdwagMgWNeBJfTksM3xg6Ag5CeTBzHgb8xKA4qZuD648YwsNAECMj8R0F7GRh+FRBS3a PaG5ogQIua8CyGcZxn1rOnuENO4rJFRBwS5AoyO1V1K6otqCUUuZ1SIpuspedRFQ8Clw 31Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777964513; x=1778569313; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ncTxOLmgEHRNxr9Ra/M7hKec3vLSGGKsocfqCJZ4FKQ=; b=PuvgHs09xT8LXzFIc4mBtQjP9/sz0bccE2abeVIk3xgdxqSTu/MlbsJ2pSH6GxN8jR 9sQEcWgh7ufSNJBQ9Z9gfNk0zyu81j3I1qStwgrGC/MdQIaX4ZT3WARW6ktyYTiZYjqj mSekQ46o2bBzKz4KHGUrB/3oj0FuB24pDzrhJVyLeRs8GrDVUAkpxp94OvSW6CS4lZEx 3b+s8BJyNKlSCNH60x5kMM056ULMgz5qGVyIdEPItvOjf+w09qNA0Onj+XzZ4CR7g/mx TYPsNbiL4FJhMA/8rJru1n84eeg0ra5xm1vFRS8uEmz1OT6TmWiOEkpqb30Tw/ba97M8 D3Pg== X-Forwarded-Encrypted: i=1; AFNElJ8XvX47gF38AkMyj26TSqIQ/yt30W2cYjFDP7sjQGHDKDk1hBZ1BrGx3QbW5vOu7J0GWyrc6+B36gSW@vger.kernel.org X-Gm-Message-State: AOJu0Yxnjkfzmt2LDlQEDPA1wGgRup9SItzP525mT0TEMtBWoXpvhZHq f+JXZbXgJhxBGr+mrkRU9iDREWodMcW7UyXwponX+zA1S+xHl1QgdL0WCNgL5EJKeVMJMJvzOix YCsmFeu0YSSYuKpFydp5aIc6L7Ci+2BRREtdnquTEP0XTVI/2jLPVELasYnFFYJ+X X-Gm-Gg: AeBDieuo4oBVbVjtw0C1iFXV16Y7RKCu992ibHqwrtCRIe4v08RV5B4ZQ4+/psZJ/4H UaIXAr4UMPlVgD1Ik3ZgyOYNO1Ofz5hpx13T7Ca6ddzekMGNouOpNIV6O0gn/eHdad55oI4K6uc YSkaxH+nJJs1RXDx+/Hs6LshdOm7JRJjoIqLu807aBOyWydXOh/h4sGZS1d0sfBRb8fBusz2xF+ 8rWyBH95H/bNoa/l0rzbdqBZghnfI7f02u4wYuJb9rYN+Zt55xGiTAXRUERJl0Y3zNZg9pyzKBw EQ1rhow0ma6WXmFkzl7s2La5Pfcbr7E5pQP2qCcEJeKPLMuVNtPUuuO71dU832SwbLspNquBHIC 4e/6SsraFpayyFUaN0Ct1wq+QFwl2Qs9G8dhtsG7KHb32aJtzJKwyC3VO4VLAMWRwrg== X-Received: by 2002:a17:90b:2b45:b0:35b:e56e:a17e with SMTP id 98e67ed59e1d1-3650ce86ae0mr11909004a91.17.1777964512631; Tue, 05 May 2026 00:01:52 -0700 (PDT) X-Received: by 2002:a17:90b:2b45:b0:35b:e56e:a17e with SMTP id 98e67ed59e1d1-3650ce86ae0mr11908963a91.17.1777964511948; Tue, 05 May 2026 00:01:51 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364ebec73aasm13840146a91.2.2026.05.05.00.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 00:01:51 -0700 (PDT) From: Vishnu Reddy Date: Tue, 05 May 2026 12:29:33 +0530 Subject: [PATCH v4 12/13] media: iris: Add platform data for glymur Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260505-glymur-v4-12-17571dbd1caa@oss.qualcomm.com> References: <20260505-glymur-v4-0-17571dbd1caa@oss.qualcomm.com> In-Reply-To: <20260505-glymur-v4-0-17571dbd1caa@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Vishnu Reddy X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777964421; l=11567; i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id; bh=GxPcM3D6fcOBB3Z1Td+dY6rhZmNKqLALfdcwQqF+Y6E=; b=sYEFADXJ7Ibvb5q5Xm2hTg1/U1oQRmhbQ7H2gHMCgVPZpuLdY0qLkWNXAsq8uIS6emBHiKYPE iP2Sh4eSzkTCzocNNaGoBJuXYrDWmQv0ujcgyUdSboblzJmk9wy6LWa X-Developer-Key: i=busanna.reddy@oss.qualcomm.com; a=ed25519; pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA1MDA2MyBTYWx0ZWRfX6TZUgJQCGuIG Y4ooCo6u6lqFnPqz7gsLqfDTHflZ0gwNAWhaBGkWwE9IyFpMZI+OY7hhvGlSmZnE4HnQ6fjsSdM aWaFhfQYphsd6i9+O6BnBiI72cPtzSZwDa3jt0OX1+hOOG9b1nXdW+hClBGWBfiYCY5DuRA2bxj EGMwgu08FD+ILrpIhzeQUXfO5BqEZ64iO38hEr4cuHjxqxPSbGI5uvp88asQ5AU/juFSsJIuSyD Gaf29B9Px9Ju5g+BKuyhONkc/6g4zFD7kxLSgXWcQ+MMLdD2lXoLcT1qbXbjhx1aZucUqLZV4xm G2xrlr6El/dTmqjXDXGWczcKpvQZAgdUmdEMwysz9Tgkn89nRqr6UFM31epFFW7xNOFU3E9jX4r d/seuj/m9+VLU8B3TdMw5vFF2Zu1tTUCdZnNckD/o1AMJunZIJPAcBNncaZtyb5U2bE7+JK9li3 xJ78uuPPLIcI57I93qQ== X-Authority-Analysis: v=2.4 cv=SPBykuvH c=1 sm=1 tr=0 ts=69f995e1 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=syK4oCsQgbaUnHKzOKsA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: SqB19oZcmgP2jEJIpZ9X1DLqvNzmue9r X-Proofpoint-ORIG-GUID: SqB19oZcmgP2jEJIpZ9X1DLqvNzmue9r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-05_02,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605050063 On glymur platform, the iris core shares most properties with the iris core on the SM8550 platform. The major difference is that glymur integrates two codec cores (vcodec0 and vcodec1), while SM8550 has only one. Add glymur specific platform data, reusing SM8550 definitions wherever applicable. Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 5 ++ .../media/platform/qcom/iris/iris_platform_gen2.c | 99 ++++++++++++++++++++++ .../platform/qcom/iris/iris_platform_glymur.c | 97 +++++++++++++++++++++ .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + 6 files changed, 223 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 6f4052b98491..677513c7c045 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -11,6 +11,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ iris_platform_gen2.o \ + iris_platform_glymur.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 502d7099085c..2003b7186480 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -30,6 +30,10 @@ struct iris_inst; #define DEFAULT_QP 20 #define BITRATE_DEFAULT 20000000 +#define VIDEO_REGION_SECURE_FW_REGION_ID 0 +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + enum stage_type { STAGE_1 = 1, STAGE_2 = 2, @@ -41,6 +45,7 @@ enum pipe_type { PIPE_4 = 4, }; +extern const struct iris_platform_data glymur_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 5862c89a4971..d11c9d1ce6b1 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" +#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8650.h" #include "iris_platform_sm8750.h" @@ -931,6 +932,104 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = { BUF_SCRATCH_2, }; +const struct iris_platform_data glymur_data = { + .get_instance = iris_hfi_gen2_get_instance, + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, + .get_vpu_buffer_size = iris_vpu_buf_size, + .vpu_ops = &iris_vpu36_ops, + .set_preset_registers = iris_set_sm8550_preset_registers, + .init_cb_devs = iris_glymur_init_cb_devs, + .deinit_cb_devs = iris_glymur_deinit_cb_devs, + .icc_tbl = sm8550_icc_table, + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl = iris_glymur_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table), + .bw_tbl_dec = sm8550_bw_table_dec, + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl = &iris_glymur_pmdomain_table, + .opp_pd_tbl = sm8550_opp_pd_table, + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl = iris_glymur_clk_table, + .clk_tbl_size = ARRAY_SIZE(iris_glymur_clk_table), + .opp_clk_tbl = iris_glymur_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xffe00000 - 1, + .fwname = "qcom/vpu/vpu36_p4_s7.mbn", + .pas_id = IRIS_PAS_ID, + .dual_core = true, + .inst_iris_fmts = platform_fmts_sm8550_dec, + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps = &platform_inst_cap_sm8550, + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), + .tz_cp_config_data = iris_glymur_tz_cp_config, + .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config), + .core_arch = VIDEO_ARCH_LX, + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config = &ubwc_config_sm8550, + .num_vpp_pipe = 4, + .max_session_count = 16, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4320) / 256) * 60, + .dec_input_config_params_default = + sm8550_vdec_input_config_params_default, + .dec_input_config_params_default_size = + ARRAY_SIZE(sm8550_vdec_input_config_params_default), + .dec_input_config_params_hevc = + sm8550_vdec_input_config_param_hevc, + .dec_input_config_params_hevc_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), + .dec_input_config_params_vp9 = + sm8550_vdec_input_config_param_vp9, + .dec_input_config_params_vp9_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), + .dec_input_config_params_av1 = + sm8550_vdec_input_config_param_av1, + .dec_input_config_params_av1_size = + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), + .dec_output_config_params = + sm8550_vdec_output_config_params, + .dec_output_config_params_size = + ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params = + sm8550_venc_input_config_params, + .enc_input_config_params_size = + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params = + sm8550_venc_output_config_params, + .enc_output_config_params_size = + ARRAY_SIZE(sm8550_venc_output_config_params), + + .dec_input_prop = sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, + .dec_output_prop_avc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, + .dec_output_prop_hevc_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, + .dec_output_prop_vp9_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, + .dec_output_prop_av1_size = + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), + + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), +}; + const struct iris_platform_data sm8550_data = { .get_instance = iris_hfi_gen2_get_instance, .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c new file mode 100644 index 000000000000..f16155b7dc99 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include "iris_core.h" +#include "iris_platform_common.h" +#include "iris_platform_glymur.h" + +const struct platform_clk_data iris_glymur_clk_table[] = { + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC1_CLK, "iface2" }, + {IRIS_VCODEC1_CLK, "vcodec1_core" }, + {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" }, +}; + +const char * const iris_glymur_clk_reset_table[] = { + "bus0", + "bus1", + "core", + "vcodec0_core", + "bus2", + "vcodec1_core", +}; + +const char * const iris_glymur_opp_clk_table[] = { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +const struct platform_pd_data iris_glymur_pmdomain_table = { + .pd_types = (enum platform_pm_domain_type []) { + IRIS_CTRL_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, + IRIS_VCODEC1_POWER_DOMAIN, + }, + .pd_names = (const char *[]) { + "venus", + "vcodec0", + "vcodec1", + }, + .pd_count = 3, +}; + +const struct tz_cp_config iris_glymur_tz_cp_config[] = { + { + .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID, + .cp_size = 0, + .cp_nonpixel_start = 0, + .cp_nonpixel_size = 0x1000000, + }, + { + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + }, + { + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x25800000, + .cp_nonpixel_size = 0xda600000, + }, +}; + +int iris_glymur_init_cb_devs(struct iris_core *core) +{ + u64 dma_mask = core->iris_platform_data->dma_mask; + const u32 fw_fid = IOMMU_FID_IRIS_FIRMWARE; + struct device *dev; + + dev = create_iris_vpu_bus_device(core->dev, "iris-firmware", dma_mask, &fw_fid); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + if (device_iommu_mapped(dev)) + core->fw_dev = dev; + else + device_unregister(dev); + + return 0; +} + +void iris_glymur_deinit_cb_devs(struct iris_core *core) +{ + if (core->fw_dev) + device_unregister(core->fw_dev); +} diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h new file mode 100644 index 000000000000..e0d07ccf658c --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_GLYMUR_H__ +#define __IRIS_PLATFORM_GLYMUR_H__ + +extern const struct platform_clk_data iris_glymur_clk_table[9]; +extern const char * const iris_glymur_clk_reset_table[6]; +extern const char * const iris_glymur_opp_clk_table[4]; +extern const struct platform_pd_data iris_glymur_pmdomain_table; +extern const struct tz_cp_config iris_glymur_tz_cp_config[3]; +int iris_glymur_init_cb_devs(struct iris_core *core); +void iris_glymur_deinit_cb_devs(struct iris_core *core); + +#endif /* __IRIS_PLATFORM_GLYMUR_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 34c981be9bc1..78e3627557e9 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -369,6 +369,10 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { + { + .compatible = "qcom,glymur-iris", + .data = &glymur_data, + }, { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, -- 2.34.1