From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B187F3DB634 for ; Tue, 5 May 2026 07:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777964485; cv=none; b=qcGzIZykumG+jRtsCPFRlaJ6MyPBALHliLJrLdY0sxuJhvMhZQSa2g2sgvrNk5KUhAkS+TfInKRdxX2PIJXbLJsv500SUvupDZfimAplz32s+eCeIY3hPO6jzxvqcnBmmXjA1WlT1xvYKH3Y5/bq6Fe1FDm8+A/uvP3QNf+S0jE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777964485; c=relaxed/simple; bh=70xFrnhgQm5w7ycFVlFn4+YpXwENh5y/BrI0x6UYWi4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rtnIKfyL0Lgx1OD2ruKYFrHRKiKA+KOjlSQQwbGTq3VWfZVNJlv9b3AMRNe+ijWbivacOcng9Gbm5/jP4MS2tO3sEAWPlPRaIe4X6/30CUNE4Fw8V5dLLM5AqCvmiBu2Phsq5AcvQMFjrq1kBtSb6HspOwY72mPPEK+EYHdJ5qA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=GB+Fp1CK; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=MDFGm67r; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="GB+Fp1CK"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="MDFGm67r" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 6456MOTj299554 for ; Tue, 5 May 2026 07:01:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= kfW5uTXNcQiD+zRKKbRk7ZRairYKuRP1etGcVg/k4f4=; b=GB+Fp1CKJN6tG3Ks rF2DqPXJY6Dq/tg+CgGX30ut1aa86Rj2iFiuQr1u9Aixr5waEh/GrJLR882kBhxL D3Yfg6AUy0zDnDhVAVGH/psLztE3RQzTSL5SHOyEt/JD2HVTFfUCo2n1E8lR11KP sAV8ysuZtyYXH8iYUy8jRTjCK4SYLi+0IfemWO8lWk6RIQATdI8QqkiLPwM39gEg 2ponL4KGzFkWjR2EFhMiDEb/zUDpyLpkrTHfl4ShFcwpsKiPcAUw3Ux9EJEa5atp d+z2jhNR+htZF2jgrmC2bfW/St3xzaMueJa+usAqxKmbSIFVnQn6RJHlMM25zOIm ClS2AA== Received: from mail-pj1-f69.google.com (mail-pj1-f69.google.com [209.85.216.69]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dxvndb8xv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 05 May 2026 07:01:22 +0000 (GMT) Received: by mail-pj1-f69.google.com with SMTP id 98e67ed59e1d1-362eb03240bso6127322a91.3 for ; Tue, 05 May 2026 00:01:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1777964482; x=1778569282; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kfW5uTXNcQiD+zRKKbRk7ZRairYKuRP1etGcVg/k4f4=; b=MDFGm67rpx15479PSxGeaXYo74k2SbBpce/Azs4kFogHAEyage7/VPu8AVl1AorqGN ZjOYgAZT4NIsx4G2Nu6Wgr46DckxoMjfLgPBRA/eHCsCEpUA9Uxn5aFCt5PbWhI4xlN3 6rMnk2W9q8F8Rd0piZtTPHqW3NQXRTw+48Vc2KG4QlCF/Yec2jPRLmUptTcXat6JOg2U AV58PFLW1Mn7YOXMR7Iuo2iWlAQCa1XVsb69W+ZOcBSLYFZ6oeEFt3IC/wne/b/Q5prz xsjlnLDXuKdxcPUvaHGZSuz8rQaewMJSlA93XiWNlRx94UwvFsKVM5EHFEJn32Bq5+r+ yEzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777964482; x=1778569282; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=kfW5uTXNcQiD+zRKKbRk7ZRairYKuRP1etGcVg/k4f4=; b=BLaKXRIOQDRGFeiIK4m8VM7OYlJAHyezqT0ToFc7iMnf6EvEuOfPy43CfcVzCmNVl4 d2W1d33UpJLYvKn7RHIOv9cwB3HRwroF5LWuZfdn4rIkHCYSwbo8U5PpdjI+J1pXrsP9 dBzV0yLvhSzNqzCc8HaJA7BRChnFoJgneWdz7bscPouNzCigqDlHjHFu3RfhnoHGd0iL pSeZBoF2+l5FxAb6zPZgw6MEp1/3maf5XrnKJq4/H3QOJig5JGtic0i9wpnUFm0gECUL ZI/Ip5Z/o7X8HHD0z8sgSYSiwKvgWfOkS/Vld9LtdOCEWCFz0bMUL4YfjOg/24GzO8gd skyA== X-Forwarded-Encrypted: i=1; AFNElJ/+C7eK28K7oicPO65bRosQAlUXFk4ouQseTPZq6gjuLkp9EISL7iLypTsmYpXSFtxTIYLxJwCgzbZi@vger.kernel.org X-Gm-Message-State: AOJu0YxM8GzDpdTWceMG4VAjF1/qM24NeW8H6QMjvD1E56aWKnW/pBUM IjkQP37M9DfINd8wdOFskxBcZcAwSwUg/cLdDs66v2QV/eNdKtv2Vkock1e3hweby2h2T00zPy2 GUZ8sF3r1H22OUJFFgp+IrsU4sXU/t0ZdJpPhjZM9nsVEyd82ovHVMDdoRHYZdA40 X-Gm-Gg: AeBDieu9V6qIl2sVeM1elxh/60UAZasd/MpB/hSfPORTTZN24dGoBRhB2i6DCNup0jo tpDundIOZkGkZyrZ/HV7l7OP3mYHYVRzNkROZjFKgV3GPugB/XYP8QpwgKZm4Mr0J7Ut09PvX8d vrPQyQs9qE8oc40numWvnWuW+UoVSIp5spkCdUH0qu/XGKssiygiSaQMtix74VR3lK++O4zRhDR +rLZTCbdn3Um+W9nSYuHXHbKIsplN7nZWnIQ0B8SVwQ2fl6TAb5fHyr4gSSWJXPp7gr+C3jXjQ/ Sj+nkfxrqJo6b99UELdbeYGlkbKm6bR20KEHnirLN55ug1zfeQ+0HdGqB1+tuIpxHaPXpbDzG2f RSIfE58ZlTPCjXbnKC4s7Q81650BqLcJc9OLt4MuuA8zL6z+k8iLNLmb4llkhkTmHTg== X-Received: by 2002:a17:90b:278f:b0:35d:a542:2dcb with SMTP id 98e67ed59e1d1-3650cdffacemr12905265a91.16.1777964482085; Tue, 05 May 2026 00:01:22 -0700 (PDT) X-Received: by 2002:a17:90b:278f:b0:35d:a542:2dcb with SMTP id 98e67ed59e1d1-3650cdffacemr12905224a91.16.1777964481507; Tue, 05 May 2026 00:01:21 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364ebec73aasm13840146a91.2.2026.05.05.00.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 May 2026 00:01:21 -0700 (PDT) From: Vishnu Reddy Date: Tue, 05 May 2026 12:29:29 +0530 Subject: [PATCH v4 08/13] media: iris: Rename clock and power domain macros to use vcodec prefix Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260505-glymur-v4-8-17571dbd1caa@oss.qualcomm.com> References: <20260505-glymur-v4-0-17571dbd1caa@oss.qualcomm.com> In-Reply-To: <20260505-glymur-v4-0-17571dbd1caa@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Vishnu Reddy X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777964421; l=16678; i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id; bh=70xFrnhgQm5w7ycFVlFn4+YpXwENh5y/BrI0x6UYWi4=; b=yHOQ0N/ThPssYi9PHbCCRgWWT4F7VXwIBmYiayUppl/N2GmnfpAThSMg97ZaFAaCzQRbQ3oxE yE9BdCRbFVACw0gsX8FDoDKXrHoj+RnqRQEUOJCL3Kr6JPUpBrXyH3e X-Developer-Key: i=busanna.reddy@oss.qualcomm.com; a=ed25519; pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok= X-Proofpoint-ORIG-GUID: LJJGLWxqcN6aT8RvBxZpveq7ixuh36Gl X-Authority-Analysis: v=2.4 cv=d9jFDxjE c=1 sm=1 tr=0 ts=69f995c2 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=kpNcZxiqwdVgWfiEekEA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: LJJGLWxqcN6aT8RvBxZpveq7ixuh36Gl X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA1MDA2MyBTYWx0ZWRfXylH4e+LQPeqa wJPcDq4uFPGiAjTDMzvvy2A8GY/w+SWG0zOcrc49Zyfmij8ILyxdn07JkV2peDwj7HUITmWziSI d+pL0gZi3Wz6XKq8LHrxf85he7LciOcC2saiDT9H5MYXDijvYm5TOw9obsPX5RwWTVMctx08nAh 8kam1YxEfeZE41h7BkPJzFNsZ98yYTK2bYAf98dQGPglK7cii0FU0Vhiu0mT5trwRGjGB31d2UC ljL0p8OdJybFy7LPt52hghC0/w8PkkxDjmF2nn00ztO+JkAqfRbbPHnb2R1tF6otgc/SUJ2eta3 ICRTaqzFwIlV2ooU2u5nw3EtZH6u7MdtEDvePU2leIBFNhoEoL/KSZKdn+AXBcpVMJH6WxjGtsY UA91gMxkXHnsojves67Aun4nlwCJEeIjh/uINumgvStfuRbXByClDBkqGd5VMeJmdFEs3lTfrqY LYUHuUJrWZugsALTU/A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-05_02,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 spamscore=0 clxscore=1015 phishscore=0 malwarescore=0 bulkscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605050063 The current clock and power domain enum names are too generic. Rename them with a vcodec prefix to make the names more meaningful and to easily accommodate vcodec1 enums for the secondary core for glymur platform. No functional changes intended. Signed-off-by: Vishnu Reddy --- .../platform/qcom/iris/iris_platform_common.h | 12 ++++---- .../media/platform/qcom/iris/iris_platform_gen1.c | 6 ++-- .../media/platform/qcom/iris/iris_platform_gen2.c | 6 ++-- .../platform/qcom/iris/iris_platform_sc7280.h | 10 +++---- .../platform/qcom/iris/iris_platform_sm8750.h | 12 ++++---- drivers/media/platform/qcom/iris/iris_vpu3x.c | 21 +++++++------- drivers/media/platform/qcom/iris/iris_vpu4x.c | 30 +++++++++++--------- drivers/media/platform/qcom/iris/iris_vpu_common.c | 33 +++++++++++----------- 8 files changed, 67 insertions(+), 63 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 55ff6137d9a9..30e9d4d288c6 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -49,14 +49,14 @@ extern const struct iris_platform_data sm8650_data; extern const struct iris_platform_data sm8750_data; enum platform_clk_type { - IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ + IRIS_AXI_VCODEC_CLK, IRIS_CTRL_CLK, IRIS_AHB_CLK, - IRIS_HW_CLK, - IRIS_HW_AHB_CLK, - IRIS_AXI1_CLK, + IRIS_VCODEC_CLK, + IRIS_VCODEC_AHB_CLK, + IRIS_AXI_CTRL_CLK, IRIS_CTRL_FREERUN_CLK, - IRIS_HW_FREERUN_CLK, + IRIS_VCODEC_FREERUN_CLK, IRIS_BSE_HW_CLK, IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, @@ -206,7 +206,7 @@ struct icc_vote_data { enum platform_pm_domain_type { IRIS_CTRL_POWER_DOMAIN, - IRIS_HW_POWER_DOMAIN, + IRIS_VCODEC_POWER_DOMAIN, IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/drivers/media/platform/qcom/iris/iris_platform_gen1.c index df8e6bf9430e..be6a631f8ede 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -284,9 +284,9 @@ static const char * const sm8250_pmdomain_table[] = { "venus", "vcodec0" }; static const char * const sm8250_opp_pd_table[] = { "mx" }; static const struct platform_clk_data sm8250_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; static const char * const sm8250_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c index 5da90d47f9c6..47c6b650f0b4 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -780,9 +780,9 @@ static const char * const sm8550_pmdomain_table[] = { "venus", "vcodec0" }; static const char * const sm8550_opp_pd_table[] = { "mxc", "mmcx" }; static const struct platform_clk_data sm8550_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, }; static const char * const sm8550_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h index 0ec8f334df67..6b783e524b81 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -16,11 +16,11 @@ static const struct bw_info sc7280_bw_table_dec[] = { static const char * const sc7280_opp_pd_table[] = { "cx" }; static const struct platform_clk_data sc7280_clk_table[] = { - {IRIS_CTRL_CLK, "core" }, - {IRIS_AXI_CLK, "iface" }, - {IRIS_AHB_CLK, "bus" }, - {IRIS_HW_CLK, "vcodec_core" }, - {IRIS_HW_AHB_CLK, "vcodec_bus" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_AHB_CLK, "bus" }, + {IRIS_VCODEC_CLK, "vcodec_core" }, + {IRIS_VCODEC_AHB_CLK, "vcodec_bus" }, }; static const char * const sc7280_opp_clk_table[] = { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h index 719056656a5b..f843f13251c5 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h @@ -11,12 +11,12 @@ static const char * const sm8750_clk_reset_table[] = { }; static const struct platform_clk_data sm8750_clk_table[] = { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_AXI1_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, + {IRIS_AXI_VCODEC_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_VCODEC_CLK, "vcodec0_core" }, + {IRIS_AXI_CTRL_CLK, "iface1" }, + {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" }, }; #endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 3dad47be78b5..834194cb5513 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -209,7 +209,7 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return 0; } @@ -218,30 +218,31 @@ static int iris_vpu35_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto err_disable_axi_clk; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_hw_free_clk; return 0; err_disable_hw_free_clk: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); err_disable_axi_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -250,8 +251,8 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) { iris_vpu33_power_off_hardware(core); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } const struct vpu_ops iris_vpu3_ops = { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/platform/qcom/iris/iris_vpu4x.c index 02e100a4045f..92c0b06bbbff 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,7 +27,8 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 { int ret; - ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], hw_mode); + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], + hw_mode); if (ret) return ret; @@ -63,7 +64,7 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode, u32 dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_DOMAIN], !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], !hw_mode); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], !hw_mode); return ret; } @@ -162,15 +163,15 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v { int ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_FREERUN_CLK); if (ret) goto disable_axi_clock; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto disable_hw_free_run_clock; @@ -198,11 +199,11 @@ static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 efuse_v disable_bse_hw_clock: iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); disable_hw_free_run_clock: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); return ret; } @@ -216,9 +217,9 @@ static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32 efuse iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } static int iris_vpu4x_power_on_hardware(struct iris_core *core) @@ -226,7 +227,8 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) u32 efuse_value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; @@ -267,7 +269,7 @@ static int iris_vpu4x_power_on_hardware(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } @@ -345,7 +347,7 @@ static void iris_vpu4x_power_off_hardware(struct iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs [IRIS_VPP0_HW_POWER_DOMAIN]); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); } static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c index f1f9e04b7c31..73c094bc4311 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -213,7 +213,7 @@ int iris_vpu_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_AHB_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); return 0; @@ -221,10 +221,10 @@ int iris_vpu_power_off_controller(struct iris_core *core) void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], false); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_VCODEC_AHB_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); } void iris_vpu_power_off(struct iris_core *core) @@ -251,7 +251,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC_CLK); if (ret) goto err_disable_power; @@ -268,7 +268,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) err_disable_ctrl_clock: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); err_disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); @@ -279,31 +279,32 @@ int iris_vpu_power_on_hw(struct iris_core *core) { int ret; - ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + ret = iris_enable_power_domains(core, + core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_CLK); if (ret) goto err_disable_power; - ret = iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); + ret = iris_prepare_enable_clock(core, IRIS_VCODEC_AHB_CLK); if (ret && ret != -ENOENT) goto err_disable_hw_clock; return 0; err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN]); return ret; } int iris_vpu_set_hwmode(struct iris_core *core) { - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); + return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VCODEC_POWER_DOMAIN], true); } int iris_vpu_switch_to_hwmode(struct iris_core *core) @@ -366,7 +367,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) disable_power: iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); @@ -383,7 +384,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) if (ret) return ret; - ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK); + ret = iris_prepare_enable_clock(core, IRIS_AXI_CTRL_CLK); if (ret) goto err_disable_power; @@ -400,7 +401,7 @@ int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) err_disable_ctrl_free_clk: iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_CTRL_CLK); err_disable_power: iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]); -- 2.34.1