From: Conor Dooley <conor@kernel.org>
To: Changhuang Liang <changhuang.liang@starfivetech.com>
Cc: Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Daniel Lezcano <daniel.lezcano@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Yixun Lan <dlan@kernel.org>,
Joel Stanley <jms@oss.tenstorrent.com>,
Drew Fustini <dfustini@oss.tenstorrent.com>,
Darshan Prajapati <darshan.prajapati@einfochips.com>,
Guodong Xu <guodong@riscstar.com>,
Michal Simek <michal.simek@amd.com>,
Junhui Liu <junhui.liu@pigmoral.tech>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
E Shattow <e@freeshell.de>, Icenowy Zheng <uwu@icenowy.me>,
Anup Patel <anup@brainfault.org>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
Ji Sheng Teoh <jisheng.teoh@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>,
Michael Zhu <michael.zhu@starfivetech.com>
Subject: Re: [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT
Date: Wed, 6 May 2026 18:44:49 +0100 [thread overview]
Message-ID: <20260506-proud-dubbed-9ab8011df899@spud> (raw)
In-Reply-To: <20260506085937.754808-5-changhuang.liang@starfivetech.com>
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On Wed, May 06, 2026 at 01:59:37AM -0700, Changhuang Liang wrote:
> From: Ley Foon Tan <leyfoon.tan@starfivetech.com>
>
> Add JHB100 base dtsi and dts. Consist of 4 Dubhe-70 cores, CLINT, PLIC,
> PMU, UART, INTC and 1GB DDR.
>
> Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> MAINTAINERS | 6 +
> arch/riscv/boot/dts/starfive/Makefile | 2 +
> arch/riscv/boot/dts/starfive/jhb100-evb1.dts | 32 ++
> arch/riscv/boot/dts/starfive/jhb100.dtsi | 337 +++++++++++++++++++
> 4 files changed, 377 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jhb100-evb1.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jhb100.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0dfad67f66c0..22e34d2ad696 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -25588,6 +25588,12 @@ F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> F: drivers/phy/starfive/phy-jh7110-pcie.c
> F: drivers/phy/starfive/phy-jh7110-usb.c
>
> +STARFIVE JHB100 DEVICETREES
> +M: Changhuang Liang <changhuang.liang@starfivetech.com>
> +L: linux-riscv@lists.infradead.org
> +S: Supported
> +F: arch/riscv/boot/dts/starfive/jhb100*
> +
> STARFIVE JHB100 EXTERNAL INTERRUPT CONTROLLER DRIVER
> M: Changhuang Liang <changhuang.liang@starfivetech.com>
> S: Supported
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 3dd1f05283f7..42841942fe54 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> +
> +dtb-$(CONFIG_ARCH_STARFIVE) += jhb100-evb1.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jhb100-evb1.dts b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
> new file mode 100644
> index 000000000000..462b6fb7953b
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100-evb1.dts
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +#include "jhb100.dtsi"
> +
> +/ {
> + model = "StarFive JHB100 EVB-1";
> + compatible = "starfive,jhb100-evb1", "starfive,jhb100";
> +
> + aliases {
> + serial6 = &uart6;
> + };
> +
> + chosen {
> + stdout-path = "serial6:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <5000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x0 0x40000000>; /* 1GB */
> + };
> +};
> +
> +&uart6 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jhb100.dtsi b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> new file mode 100644
> index 000000000000..4133ba1f45b4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jhb100.dtsi
> @@ -0,0 +1,337 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (c) 2024-2026 StarFive Technology Co., Ltd.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + compatible = "starfive,jhb100";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "starfive,dubhe-70", "riscv";
> + reg = <0x0>;
> + riscv,isa = "rv64imafdcbh";
Please just remove this property.
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "h", "zba", "zbb",
> + "zbc", "zbs", "zicbom", "zicbop", "zicboz", "zicntr",
> + "zicond", "zicsr", "zifencei", "zihintpause",
> + "zihpm", "svinval", "svnapot", "sscofpmf";
> + riscv,cbom-block-size = <64>;
> + riscv,cbop-block-size = <64>;
> + riscv,cboz-block-size = <64>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <512>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <16>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <512>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <24>;
> + mmu-type = "riscv,sv48";
> + next-level-cache = <&l2c0>;
> + tlb-split;
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + };
Each cpu is in a different cluster? Interesting, suppose it makes sense
when you have different l2 caches. What other resources are not shared?
Do they have different cpu clocks too etc?
> +
> + cluster1 {
> + core0 {
> + cpu = <&cpu1>;
> + };
> + };
> +
> + cluster2 {
> + core0 {
> + cpu = <&cpu2>;
> + };
> + };
> +
> + cluster3 {
> + core0 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + l2c0: cache-controller-0 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l2c1: cache-controller-1 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l2c2: cache-controller-2 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l2c3: cache-controller-3 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <2048>;
> + cache-size = <0x20000>;
> + cache-unified;
> + next-level-cache = <&l3_cache>;
> + };
> +
> + l3_cache: cache-controller-4 {
> + compatible = "cache";
> + cache-block-size = <64>;
> + cache-level = <3>;
> + cache-sets = <1024>;
> + cache-size = <0x20000>;
> + cache-unified;
> + };
> + };
> + clk_uart: clock-25000000 {
> + compatible = "fixed-clock"; /* Initial clock handler for UART */
What does this comment mean?
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + interrupt-parent = <&plic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-ranges;
> + ranges;
> +
> + clint: timer@2000000 {
> + compatible = "starfive,jhb100-clint", "sifive,clint0";
> + reg = <0x0 0x02000000 0x0 0x10000>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>;
> + };
> +
> + plic: interrupt-controller@c000000 {
> + compatible = "starfive,jhb100-plic", "sifive,plic-1.0.0";
> + reg = <0x0 0x0c000000 0x0 0x4000000>;
> + riscv,ndev = <400>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <0>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>;
> + };
> +
> + bus_nioc: bus_nioc {
jhb100-evb1.dtb: bus_nioc (simple-bus): $nodename:0: 'bus_nioc' does not match '^([a-z][a-z0-9\\-]+-bus|bus|localbus|soc|axi|ahb|apb)(@.+)?$'
from schema $id: http://devicetree.org/schemas/simple-bus.yaml
Cheers,
Conor.
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + dma-noncoherent;
> + dma-ranges = <0x4 0x00000000 0x0 0x40000000 0x2 0x0>,
> + <0x4 0x00000000 0x4 0x00000000 0x2 0x0>;
> + ranges;
> +
> + uart6: serial@11982000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x0 0x11982000 0x0 0x400>;
> + clocks = <&clk_uart>, <&clk_uart>;
> + clock-names = "baudclk", "apb_pclk";
> + interrupt-parent = <&intc>;
> + interrupts = <26>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + intc: interrupt-controller@13220000 {
> + compatible = "starfive,jhb100-intc";
> + reg = <0x0 0x13220000 0x0 0x80>;
> + interrupts = <1>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
> +};
> --
> 2.25.1
>
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prev parent reply other threads:[~2026-05-06 17:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-06 8:59 [PATCH v2 0/4] Initial device tree support for StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 1/4] dt-bindings: riscv: Add StarFive Dubhe-70 compatibles Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 2/4] dt-bindings: interrupt-controller: Add StarFive JHB100 plic Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 3/4] dt-bindings: riscv: Add StarFive JHB100 SoC Changhuang Liang
2026-05-06 8:59 ` [PATCH v2 4/4] riscv: dts: starfive: jhb100: Add JHB100 base DT Changhuang Liang
2026-05-06 17:44 ` Conor Dooley [this message]
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