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Wed, 06 May 2026 12:34:05 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Wed, 06 May 2026 22:33:20 +0300 Subject: [PATCH v8 3/6] ARM: zte: Add support for zx29 low level debug Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260506-send-v8-3-f1bdf3243b34@gmail.com> References: <20260506-send-v8-0-f1bdf3243b34@gmail.com> In-Reply-To: <20260506-send-v8-0-f1bdf3243b34@gmail.com> To: Jonathan Corbet , Shuah Khan , Russell King , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Arnd Bergmann , Krzysztof Kozlowski , Alexandre Belloni , Linus Walleij , Drew Fustini , Greg Kroah-Hartman , Jiri Slaby Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, soc@lists.linux.dev, linux-serial@vger.kernel.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 This is based on the removed zx29 code. A separate (more complicated) patch will re-add the register map to the pl011 serial driver. Reviewed-by: Linus Walleij Signed-off-by: Stefan Dösinger --- Patch changelog: v8: Adjust UART01x_FR_BUSY to match the different ZX UART registers (Sashiko). I am unsure about UART01x_FR_TXFF and my boards do not expose flow control pins to allow me to test if it works. I am unsure about the virtual address. It doesn't seem to matter, as long as it is a valid address. This address is based on the old removed code. Is there a rule-of-thumb physical to virtual mapping I can use to give a sensible default value? --- arch/arm/Kconfig.debug | 12 ++++++++++++ arch/arm/include/debug/pl01x.S | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 366f162e147d..98d8a5a60048 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1331,6 +1331,16 @@ choice This option selects UART0 on VIA/Wondermedia System-on-a-chip devices, including VT8500, WM8505, WM8650 and WM8850. + config DEBUG_ZTE_ZX + bool "Kernel low-level debugging via zx29 UART" + select DEBUG_UART_PL01X + depends on ARCH_ZTE + help + Say Y here if you are enabling ZTE zx297520v3 SOC and need + debug UART support. This UART is a PL011 with different + register addresses. The UART for boot messages on zx29 boards + is usually UART1 and is operating at 921600 8N1. + config DEBUG_ZYNQ_UART0 bool "Kernel low-level debugging on Xilinx Zynq using UART0" depends on ARCH_ZYNQ @@ -1545,6 +1555,7 @@ config DEBUG_UART_8250 config DEBUG_UART_PHYS hex "Physical base address of debug UART" + default 0x01408000 if DEBUG_ZTE_ZX default 0x01c28000 if DEBUG_SUNXI_UART0 default 0x01c28400 if DEBUG_SUNXI_UART1 default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 @@ -1701,6 +1712,7 @@ config DEBUG_UART_VIRT default 0xf31004c0 if DEBUG_MESON_UARTAO default 0xf4090000 if DEBUG_LPC32XX default 0xf4200000 if DEBUG_GEMINI + default 0xf4708000 if DEBUG_ZTE_ZX default 0xf6200000 if DEBUG_PXA_UART1 default 0xf7000000 if DEBUG_SUN9I_UART0 default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S index c7e02d0628bf..9dcdeed2357d 100644 --- a/arch/arm/include/debug/pl01x.S +++ b/arch/arm/include/debug/pl01x.S @@ -8,6 +8,15 @@ */ #include +#ifdef CONFIG_DEBUG_ZTE_ZX +#undef UART01x_DR +#undef UART01x_FR +#undef UART01x_FR_BUSY +#define UART01x_DR 0x04 +#define UART01x_FR 0x14 +#define UART01x_FR_BUSY (1<<8) +#endif + #ifdef CONFIG_DEBUG_UART_PHYS .macro addruart, rp, rv, tmp ldr \rp, =CONFIG_DEBUG_UART_PHYS -- 2.53.0