[PATCH v2 09/13] arm64: dts: ti: k3-j721e-beagleboneai64: fix USB clocking for compliance

Siddharth Vadapalli
2026-05-06T14:09:35Z

Fixes: fae14a1cb8dd ("arm64: dts: ti: Add k3-j721e-beagleboneai64")
Cc: <stable@vger.kernel.org>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

v1:
https://lore.kernel.org/r/20260505110631.1144200-10-s-vadapalli@ti.com/
No changes since v1.

.../arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 15 +++++++++++++++
1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index 8040b6528c18..1e87c6cf146a 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -578,6 +578,11 @@ &serdes_ln_ctrl {
&serdes_wiz3 {
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_LOW>;
typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
+ ti,core-clk-sel = <1>; /* Select internal reference clock */
+ ti,ssc-enable; /* Enable SSC */
+ ti,ssc-type = <1>; /* 1 for Downspread */
+ ti,ssc-frequency-hz = <33000>; /* 33 KHz */
+ ti,ssc-depth-per-mil = <5>; /* 0.5% depth */
};

&serdes3 {
@@ -586,6 +591,7 @@ serdes3_usb_link: phy@0 {
cdns,num-lanes = <2>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
+ cdns,ssc-mode = <2>; /* 2 for internal SSC */
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
};
};
@@ -621,12 +627,21 @@ &usb0 {
phy-names = "cdns3,usb3-phy";
};

+&serdes_wiz2 {
+ ti,core-clk-sel = <1>; /* Select internal reference clock */
+ ti,ssc-enable; /* Enable SSC */
+ ti,ssc-type = <1>; /* 1 for Downspread */
+ ti,ssc-frequency-hz = <33000>; /* 33 KHz */
+ ti,ssc-depth-per-mil = <5>; /* 0.5% depth */
+};
+
&serdes2 {
serdes2_usb_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
+ cdns,ssc-mode = <2>; /* 2 for internal SSC */
resets = <&serdes_wiz2 2>;
};
};
--
2.51.1