[PATCH v2 02/13] arm64: dts: ti: k3-am642-phyboard-electra-rdk: fix USB clocking for compliance

Siddharth Vadapalli
2026-05-06T14:08:43Z

Fixes: c48ac0efe6d7 ("arm64: dts: ti: Add support for phyBOARD-Electra-AM642")
Cc: <stable@vger.kernel.org>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

v1:
https://lore.kernel.org/r/20260505110631.1144200-3-s-vadapalli@ti.com/
No changes since v1.

arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
index 793538f94942..a85d7d08bd1b 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
@@ -439,12 +439,21 @@ &sdhci1 {
status = "okay";
};

+&serdes_wiz0 {
+ ti,core-clk-sel = <1>; /* Select internal reference clock */
+ ti,ssc-enable; /* Enable SSC */
+ ti,ssc-type = <1>; /* 1 for Downspread */
+ ti,ssc-frequency-hz = <33000>; /* 33 KHz */
+ ti,ssc-depth-per-mil = <5>; /* 0.5% depth */
+};
+
&serdes0 {
serdes0_pcie_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
cdns,phy-type = <PHY_TYPE_USB3>;
+ cdns,ssc-mode = <2>; /* 2 for internal SSC */
resets = <&serdes_wiz0 1>;
};
};
--
2.51.1