From: Xilin Wu <sophon@radxa.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Xilin Wu <sophon@radxa.com>
Subject: [PATCH] arm64: dts: qcom: sc8280xp: Move PHY, PERST, and Wake GPIOs to PCIe port nodes
Date: Thu, 07 May 2026 22:16:07 +0800 [thread overview]
Message-ID: <20260507-8280-move-perst-wake-v1-1-5b33cef2d807@radxa.com> (raw)
Since describing the PCIe PHY directly under the RC node is now
deprecated, move the references to the respective PCIe port nodes.
And also move the PCIe PERST and wake GPIOs from the controller nodes to
the corresponding PCIe port nodes on sc8280xp-based platforms:
- sa8295p-adp
- sa8540p-ride
- sc8280xp-crd
- sc8280xp-huawei-gaokun3
- sc8280xp-lenovo-thinkpad-x13s
- sc8280xp-microsoft-arcata
- sc8280xp-microsoft-blackrock
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 32 ++++++++++++++--------
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 16 +++++++----
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 22 +++++++++------
.../boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 14 ++++++----
.../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++++------
.../boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 22 +++++++++------
.../boot/dts/qcom/sc8280xp-microsoft-blackrock.dts | 14 ++++++----
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++----------
8 files changed, 95 insertions(+), 72 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
index d28d69162427..512de3597581 100644
--- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
+++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts
@@ -453,15 +453,17 @@ &mdss1_dp3_phy {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -472,15 +474,17 @@ &pcie2a_phy {
&pcie3a {
num-lanes = <2>;
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -489,15 +493,17 @@ &pcie3a_phy {
};
&pcie3b {
- perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie3b_default>;
status = "okay";
};
+&pcie3b_port0 {
+ reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
+};
+
&pcie3b_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -506,15 +512,17 @@ &pcie3b_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie4_default>;
status = "okay";
};
+&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+};
+
&pcie4_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 44177e9b64b5..83d5f1d9e79b 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -366,15 +366,17 @@ &pcie2a {
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
<0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "disabled";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
+};
+
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
@@ -387,15 +389,17 @@ &pcie3a {
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
<0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
-
pinctrl-names = "default";
pinctrl-0 = <&pcie3a_default>;
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>;
+};
+
&pcie3a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index c53e00cae465..777b253d2e76 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -628,9 +628,6 @@ keyboard@68 {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -646,10 +643,12 @@ &pcie2a_phy {
status = "okay";
};
-&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+&pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@@ -665,12 +664,14 @@ &pcie3a_phy {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@@ -687,6 +688,9 @@ &pcie4_phy {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
index 9819454abe13..96c7bcbe9bbc 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts
@@ -739,9 +739,6 @@ &mdss0_dp1_out {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -757,12 +754,14 @@ &pcie2a_phy {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -772,6 +771,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index d84ca010ab9d..0ef98a36acfd 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -933,9 +933,6 @@ keyboard@68 {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -951,10 +948,12 @@ &pcie2a_phy {
status = "okay";
};
-&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+&pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-names = "default";
@@ -970,12 +969,14 @@ &pcie3a_phy {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-names = "default";
@@ -985,6 +986,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
index f2b4470d4407..3d589f05b90e 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
@@ -486,9 +486,6 @@ &mdss0_dp1_out {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -504,10 +501,12 @@ &pcie2a_phy {
status = "okay";
};
-&pcie3a {
- perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+&pcie3a {
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie3a_default>;
@@ -523,12 +522,14 @@ &pcie3a_phy {
status = "okay";
};
+&pcie3a_port0 {
+ reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -538,6 +539,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
index 00bbeeef6f14..7f82d583c3f7 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts
@@ -624,9 +624,6 @@ &mdss0_dp2_phy {
};
&pcie2a {
- perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie2a_default>;
@@ -642,12 +639,14 @@ &pcie2a_phy {
status = "okay";
};
+&pcie2a_port0 {
+ reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+};
+
&pcie4 {
max-link-speed = <2>;
- perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wlan>;
pinctrl-0 = <&pcie4_default>;
@@ -657,6 +656,9 @@ &pcie4 {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 761f229e8f47..40577173053d 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -2220,9 +2220,6 @@ pcie4: pcie@1c00000 {
power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie4_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie4_port0: pcie@0 {
@@ -2230,6 +2227,8 @@ pcie4_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie4_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2331,9 +2330,6 @@ pcie3b: pcie@1c08000 {
power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie3b_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie3b_port0: pcie@0 {
@@ -2341,6 +2337,8 @@ pcie3b_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie3b_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2442,9 +2440,6 @@ pcie3a: pcie@1c10000 {
power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie3a_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie3a_port0: pcie@0 {
@@ -2452,6 +2447,8 @@ pcie3a_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie3a_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2556,9 +2553,6 @@ pcie2b: pcie@1c18000 {
power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie2b_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie2b_port0: pcie@0 {
@@ -2566,6 +2560,8 @@ pcie2b_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie2b_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2667,9 +2663,6 @@ pcie2a: pcie@1c20000 {
power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
- phys = <&pcie2a_phy>;
- phy-names = "pciephy";
-
status = "disabled";
pcie2a_port0: pcie@0 {
@@ -2677,6 +2670,8 @@ pcie2a_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
+ phys = <&pcie2a_phy>;
+
#address-cells = <3>;
#size-cells = <2>;
ranges;
---
base-commit: 735d2f48cadaa9a87e7c7601667878de70c771c5
change-id: 20260507-8280-move-perst-wake-fba54208da6d
Best regards,
--
Xilin Wu <sophon@radxa.com>
next reply other threads:[~2026-05-07 14:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-07 14:16 Xilin Wu [this message]
2026-05-11 11:29 ` [PATCH] arm64: dts: qcom: sc8280xp: Move PHY, PERST, and Wake GPIOs to PCIe port nodes Konrad Dybcio
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