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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bae78751fesm2530455ad.73.2026.05.07.10.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 10:08:34 -0700 (PDT) From: Kathiravan Thirumoorthy Subject: [PATCH v3 0/4] Add minimal boot support for Qualcomm IPQ9650 SoC Date: Thu, 07 May 2026 22:38:26 +0530 Message-Id: <20260507-ipq9650_boot_to_shell-v3-0-62742b49c991@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAArH/GkC/3WOQQ6CMBBFr0K6tqSlFMSV9zCEQBmlBih0CtEQ7 m4BE1duJnmTP//NQhCsBiSXYCEWZo3a9B7EKSCqKfsHUF17JhGLEiYEo3oYs0SyojLGFc4U2ED bUi4zFqW1jM9KEX87WLjr1957yw/GqXqCclvZN2FhnLzQ/WKNRmfse/9m5tv2EMdc/hHPnDJai RSqWImS1/xqEMNxKltlui70g+Trun4ALWXOVugAAAA= X-Change-ID: 20260330-ipq9650_boot_to_shell-159027d548cc To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Krzysztof Kozlowski X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778173710; l=2791; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=iqVsyYlA+PkqKzWx8JHLx4T3/K9tKA/nyf40GvGZSeI=; b=+2WUeZSlDg8W4QeAuP+zv3zblPxROagGLKrDwEnEOdN5dBrguD7qg8fiS0t/iqPaSztHjbjk4 4C76MlY9VDkAhHTaSpkVja1iGtM4dWC44oPATfjaY6E01++a3nUX72v X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Authority-Analysis: v=2.4 cv=EoPiaycA c=1 sm=1 tr=0 ts=69fcc715 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=bC-a23v3AAAA:8 a=YURS4O9UCPS1-Wi1IM0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-ORIG-GUID: zZZA11_Xy0CMGNLj9YyZPZk1wNx48VO5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDE3MiBTYWx0ZWRfX44uAqdlCfEW5 0hHYI9OihmftPwPWYIsYGWkZ6new5muIeYXHuqhS+gXaT2iluPf9COx7sy1xQ3tg5PbTTPXef5d kC7heFrvMkRyvv8gGJJjNNv5dzNp//0WYFZ3N7N5IYAr7ap/9AQkV4/cQK6ZfUWy2sOlCliBa0u NzMRQjoikxFaKaiWjmcGRUIGuLYWvdTCy6T7YqFpo2bxWp1gAcI3vG0p936HbxGZtIrA9GNLV2K 7XJpVQxqX/4hD5236BSw2KolWslJADWlaGFKWoNluh//cWuOWywY4yaBxRP4zIDqi/FpZkZA01N aCslQ/1RBYLtPMGCatDt3ApXk+4ljYfqp7hXOrWWMoufHNhR39nHhM3w0uFeTmQtoVgWZK+6TaW KeGyfPJcFMRK0ZEgqNKcUzTXjC9lBWVTE8tMdm90aVbWg410XNkrxT39XxmFTHPD6vZAWlei1YC 6kEA5L9rnULcjBPL94g== X-Proofpoint-GUID: zZZA11_Xy0CMGNLj9YyZPZk1wNx48VO5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070172 Qualcomm IPQ9650 is a networking SoC targeted at routers, gateways, and access points. This change adds minimal support required to boot the IPQ9650 RDP488 board. Compared to earlier IPQ SoCs, IPQ9650 features a heterogeneous CPU configuration with four Cortex-A55 cores and one Cortex-A78 core, a 2 MB shared L3 cache, SMMU support, IPCC, five PCIe Gen3 controllers, an integrated CDSP for task offloading, enhanced PPE capabilities, and DDR5 memory support. More information can be found at the product page: https://docs.qualcomm.com/doc/87-96766-1/87-96766-1_REV_AA_Qualcomm_Dragonwing_NPro_A8_Elite_Platform_Product_Brief.pdf Signed-off-by: Kathiravan Thirumoorthy --- Changes in v3: - Added \n before the status property - Rebased on next-20260507 - Dropped the REFGEN, PRIMESS clocks from the bindings and the GCC driver since the ownership of these clocks are in discussion. It will be added back if Linux needs to play with those clocks. - Link to v2: https://lore.kernel.org/all/20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com/ Changes in v2: - Collected the R-b tags - Add the ARM64 dependency to the GCC driver and enable it by default to align with Krzysztof's effort to cleanup the defconfig - Updated the GICv3 interrupt-cells to 4 and added the ppi-partitions and hooked up with the PMU instances. - Made the labels to lower case and kept the \n before status property - Dropped the defconfig patch - Link to v1: https://patch.msgid.link/20260415-ipq9650_boot_to_shell-v1-0-b37eb4c3a1d1@oss.qualcomm.com --- Kathiravan Thirumoorthy (4): dt-bindings: clock: add Qualcomm IPQ9650 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC dt-bindings: qcom: add IPQ9650 boards arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support Documentation/devicetree/bindings/arm/qcom.yaml | 5 + .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 + arch/arm64/boot/dts/qcom/ipq9650.dtsi | 377 +++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9650.c | 3445 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 172 + include/dt-bindings/reset/qcom,ipq9650-gcc.h | 215 ++ 10 files changed, 4373 insertions(+) --- base-commit: 17c7841d09ee7d33557fd075562d9289b6018c90 change-id: 20260330-ipq9650_boot_to_shell-159027d548cc Best regards, -- Kathiravan Thirumoorthy