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Thu, 7 May 2026 07:00:01 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG2PEPF000B66D0.mail.protection.outlook.com (10.167.240.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9891.9 via Frontend Transport; Thu, 7 May 2026 07:00:00 +0000 Received: from local (unknown [172.16.64.130]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 0281040A5A01; Thu, 7 May 2026 15:00:00 +0800 (CST) From: Devin Li To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cix-kernel-upstream@cixtech.com Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, guoyin.chen@cixtech.com, robin.wang@cixtech.com, hong.guo@cixtech.com, Devin.Li@cixtech.com Subject: [PATCH v2] arm64: dts: cix: Add CPU idle states for Sky1 Date: Thu, 7 May 2026 14:59:56 +0800 Message-ID: <20260507065956.3900087-1-Devin.Li@cixtech.com> X-Mailer: git-send-email @GIT_VERSION@ Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66D0:EE_|SI6PR06MB7218:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: e1c666c8-acc5-47d4-22e8-08deac06420b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|18002099003|56012099003; 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Three idle states are defined: - CPU_SLEEP_0: Core idle state for A520 cores (psci-suspend-param 0x0010000), entry-latency 34us, exit-latency 100us - CPU_SLEEP_1: Core idle state for A720 cores (psci-suspend-param 0x10000), entry-latency 31us, exit-latency 79us - CLUSTER_SLEEP_0: Cluster idle state shared by all cores (psci-suspend-param 0x1010000), entry-latency 41us, exit-latency 104us A520 cores (cpu0-3) reference CPU_SLEEP_0 and CLUSTER_SLEEP_0, while A720 cores (cpu4-11) reference CPU_SLEEP_1 and CLUSTER_SLEEP_0. Signed-off-by: Devin Li --- Notes: Change for v2: - Use real name format "Devin Li" - link to v1: https://lore.kernel.org/all/20260424043436.162009-1-Devin.Li@cixtech.com/ arch/arm64/boot/dts/cix/sky1.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi index bb5cfb1f2113..0611098b5f05 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -23,6 +23,7 @@ cpu0: cpu@0 { reg = <0x0 0x0>; device_type = "cpu"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu1: cpu@100 { @@ -31,6 +32,7 @@ cpu1: cpu@100 { reg = <0x0 0x100>; device_type = "cpu"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu2: cpu@200 { @@ -39,6 +41,7 @@ cpu2: cpu@200 { reg = <0x0 0x200>; device_type = "cpu"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu3: cpu@300 { @@ -47,6 +50,7 @@ cpu3: cpu@300 { reg = <0x0 0x300>; device_type = "cpu"; capacity-dmips-mhz = <403>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; }; cpu4: cpu@400 { @@ -55,6 +59,7 @@ cpu4: cpu@400 { reg = <0x0 0x400>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu5: cpu@500 { @@ -63,6 +68,7 @@ cpu5: cpu@500 { reg = <0x0 0x500>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu6: cpu@600 { @@ -71,6 +77,7 @@ cpu6: cpu@600 { reg = <0x0 0x600>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu7: cpu@700 { @@ -79,6 +86,7 @@ cpu7: cpu@700 { reg = <0x0 0x700>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu8: cpu@800 { @@ -87,6 +95,7 @@ cpu8: cpu@800 { reg = <0x0 0x800>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu9: cpu@900 { @@ -95,6 +104,7 @@ cpu9: cpu@900 { reg = <0x0 0x900>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu10: cpu@a00 { @@ -103,6 +113,7 @@ cpu10: cpu@a00 { reg = <0x0 0xa00>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu11: cpu@b00 { @@ -111,6 +122,7 @@ cpu11: cpu@b00 { reg = <0x0 0xb00>; device_type = "cpu"; capacity-dmips-mhz = <1024>; + cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_0>; }; cpu-map { @@ -153,6 +165,35 @@ core11 { }; }; }; + + idle-states { + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <34>; + exit-latency-us = <100>; + min-residency-us = <3000>; + }; + + CPU_SLEEP_1: cpu-sleep-1 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010000>; + local-timer-stop; + entry-latency-us = <31>; + exit-latency-us = <79>; + min-residency-us = <3000>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1010000>; + local-timer-stop; + entry-latency-us = <41>; + exit-latency-us = <104>; + min-residency-us = <4000>; + }; + }; }; firmware { -- 2.49.0