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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f88885b87dsm5033122eec.21.2026.05.08.16.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 16:31:26 -0700 (PDT) From: Matthew Leung Date: Fri, 08 May 2026 23:31:20 +0000 Subject: [PATCH 05/10] phy: qcom-qmp: pcs-pcie: Add v10 register offsets Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260508-hawi-phy-pcie-v1-5-237b894353fc@oss.qualcomm.com> References: <20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com> In-Reply-To: <20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778283082; l=1757; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=8Pt1Iry46S+aeKxOUquDig1kaHN7zoPCKWm77OKh1o0=; b=m2ywsU2DGNXxUhUIuOPFjA9wk8TahhnDTjaoCybhJUMJPNrznlkKV6dCqB9AbtQhI9wBb8wYP ZmYnKlb24CKAsDz5ZyEvpSRVU5/3lLltLW8TdnbI4MXydoSx5OR1gs+ X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDIzMiBTYWx0ZWRfX98cUctWqbxKK mLZXOEHj1FYRK9K94jtAd5A+i1RI/bVBzW2iZlLAiKGSUXHjdTqFlWXsoyLt3NuKjkMkvvLTB6W xDwMIWV0xGuTHEjy26pGL0nwJzznCg4YbeJUxR+KMcPap6P/+mTcyXocTloqAC95JYexxn3YG8D 9wkc6FU2G+RO2vGa+zA9FrxGAYzuT/VCDxFPGtC3iQ+6CE+QAIfKl8C86+DJFJX6EVeUfD5AJXg lt+VPF0hoOnbaoj8xCeMYqGDgYyagJuvSQANeLKG+gXf4nc4c9sUNYOXbGmTxP2Yaa4vbKEuMgL giiTnsH1W2+TKeJx4tQrUU0ThaQNKszYc9b5b3QmExkqGEyNKPizODPq1oZ+1QH0VrLR1jVUg4e bTcVPmk800PMzolOm+uLxP2BGk0VM8nlvk3fvpCOmha5SFBDyQXQYJOuRkV+uZrz+SwnwmgKuRy sgBPLOFtHmV6aUqAiDQ== X-Authority-Analysis: v=2.4 cv=LORWhpW9 c=1 sm=1 tr=0 ts=69fe7250 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=a_mrqaUjlmxG8iE0lbgA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: DOLlN87hOFY0SQTZrWWqSy2mf0WOBlbB X-Proofpoint-GUID: DOLlN87hOFY0SQTZrWWqSy2mf0WOBlbB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080232 Hawi SoC uses QMP phy with version v10 for PCIe Gen3 x2. Add the new PCS PCIe specific offsets in a dedicated header file. Signed-off-by: Matthew Leung --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index fed2fc9bb311..ba17e53d000f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -40,6 +40,7 @@ #include "phy-qcom-qmp-qserdes-com-v8.h" #include "phy-qcom-qmp-pcs-pcie-v8.h" #include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h" +#include "phy-qcom-qmp-pcs-pcie-v10.h" #define PHY_INIT_COMPLETE_TIMEOUT 10000 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h new file mode 100644 index 000000000000..2cdcc211bd93 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V10_H_ + +/* Only for QMP V10 PHY - PCIE PCS registers */ +#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4 0x014 +#define QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE 0x020 +#define QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS 0x094 +#define QPHY_PCIE_V10_PCS_EQ_CONFIG1 0x0a4 +#define QPHY_PCIE_V10_PCS_RXEQEVAL_TIME 0x0f4 +#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6 0x0f8 + +#endif -- 2.34.1