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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f88885b87dsm5033122eec.21.2026.05.08.16.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 16:31:27 -0700 (PDT) From: Matthew Leung Date: Fri, 08 May 2026 23:31:21 +0000 Subject: [PATCH 06/10] phy: qcom-qmp: qserdes-com: Add v10.60 register offsets Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260508-hawi-phy-pcie-v1-6-237b894353fc@oss.qualcomm.com> References: <20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com> In-Reply-To: <20260508-hawi-phy-pcie-v1-0-237b894353fc@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778283082; l=3662; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=l+CJCriIHCqSTKfqB3yNlnKfu4zi16GuU5MaRzEG1I0=; b=SQPGvg0Vr7HJhUFr2y1XzSHCV/4M0ZuKpm/xAp2rbdav4FYRezMMGfW6djNo9UDc6Q1udRlzM wBb7DPMmy8sAgTTaPdTZx8UOt9oAOCceVxbT6skE1QgVtk14BXGR+ap X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDIzMiBTYWx0ZWRfX6DfECkXlY+/X uw2JJmtt9figOEHUy2pEjfOrMPQnHYcIkdAeHYBOm0Bl4WicjsJEnH8wd5J6LI5z47yupS9/tgx lWYBvsEnGBE/mdFobpl7+/17sZ2TnVjEIedZY8Y7024rwmyRUUJxwgBb2KgsWc8z8ol5JgMaT87 /eSULnljn6LsenzszyR3mt9QSit3SzeyETC56ncC9zmWbpDu54NJZw1ui/LR7Y/7z4gH/Hjxw50 fm56LwrvXLQun83UONJkkNgImW8omdPLUp9AsG5/fryS1bN25Lg1WnNAhPCwyaawzCjUdC80eka UhDpqP2/IeCRm7zxUPQ/6i1lInr5dnoo7YjGSXUSO1zGZeeC//dgyiv1QbhtT5peyjuntNLP+OA 2ttR7BMBdXIpK5m83+vOSQVI78HYSzDafAVyc+S/feOpc9DC6UmLxfh2lixOBTy5T7wf9mTP7C1 jW8JY8eCIOd85BIIOiQ== X-Authority-Analysis: v=2.4 cv=LORWhpW9 c=1 sm=1 tr=0 ts=69fe7251 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=MN0C-abDVP1yrleAEAUA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-ORIG-GUID: BrTQMrieo3zUPKrsfs-jtPosDPHx6_19 X-Proofpoint-GUID: BrTQMrieo3zUPKrsfs-jtPosDPHx6_19 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 spamscore=0 malwarescore=0 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080232 Hawi SoC uses v10.60 register definitions for PCIe Gen4 x1. Add the new QSERDES-COM offsets in a dedicated header file. Signed-off-by: Matthew Leung --- .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h | 55 ++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 2 + 2 files changed, 57 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h new file mode 100644 index 000000000000..39351bef8b63 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_ + +/* Only for QMP V10_60 PHY - QSERDES COM registers */ +#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10 +#define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V10_60_COM_DEC_START_MODE1 0x28 +#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c +#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70 +#define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c +#define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V10_60_COM_DEC_START_MODE0 0x88 +#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c +#define QSERDES_V10_60_COM_BG_TIMER 0xbc +#define QSERDES_V10_60_COM_SSC_PER1 0xcc +#define QSERDES_V10_60_COM_SSC_PER2 0xd0 +#define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc +#define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0 +#define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4 +#define QSERDES_V10_60_COM_PLL_IVCO 0xf4 +#define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120 +#define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V10_60_COM_CLK_SELECT 0x164 +#define QSERDES_V10_60_COM_CORE_CLK_EN 0x170 +#define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V10_60_COM_CMN_MISC1 0x184 +#define QSERDES_V10_60_COM_CMN_MODE 0x188 +#define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198 +#define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 7af77572970e..85da2581ef90 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -42,6 +42,8 @@ #include "phy-qcom-qmp-qserdes-com-v10.h" #include "phy-qcom-qmp-qserdes-txrx-v10.h" +#include "phy-qcom-qmp-qserdes-com-v10_60.h" + #include "phy-qcom-qmp-qserdes-pll.h" #include "phy-qcom-qmp-pcs-v2.h" -- 2.34.1