From: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Subject: [PATCH] arm64: dts: qcom: kaanapali: Switch SCMI perf protocol to use power-domain-cells
Date: Fri, 8 May 2026 13:57:28 +0530 [thread overview]
Message-ID: <20260508082729.37674-1-mukesh.ojha@oss.qualcomm.com> (raw)
The SCMI protocol@13 (Performance Domain Management) node was using
performance/power domain, not a clock. This was using the older
mechanism for passing the SCMI performance domain index to
scmi-cpufreq, which predates the #power-domain-cells support added
in commit 92b2028b00ff ("cpufreq: scmi: Add support to parse
domain-id using #power-domain-cells").
Switch to #power-domain-cells to match all other Qualcomm platforms
(sm8750, glymur, hamoa) and align with the semantically correct
representation.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 44 ++++++++++---------------
1 file changed, 18 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7cc326aa1a1a..dab1ca696741 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -45,9 +45,8 @@ cpu0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd0>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 0>;
+ power-domains = <&cpu_pd0>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
l2_0: l2-cache {
compatible = "cache";
@@ -62,9 +61,8 @@ cpu1: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd1>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 0>;
+ power-domains = <&cpu_pd1>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
};
cpu2: cpu@200 {
@@ -73,9 +71,8 @@ cpu2: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd2>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 0>;
+ power-domains = <&cpu_pd2>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
};
cpu3: cpu@300 {
@@ -84,9 +81,8 @@ cpu3: cpu@300 {
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd3>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 0>;
+ power-domains = <&cpu_pd3>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
};
cpu4: cpu@400 {
@@ -95,9 +91,8 @@ cpu4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd4>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 0>;
+ power-domains = <&cpu_pd4>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
};
cpu5: cpu@500 {
@@ -106,9 +101,8 @@ cpu5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&l2_0>;
- power-domains = <&cpu_pd5>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 0>;
+ power-domains = <&cpu_pd5>, <&scmi_perf 0>;
+ power-domain-names = "psci", "perf";
};
cpu6: cpu@10000 {
@@ -117,9 +111,8 @@ cpu6: cpu@10000 {
reg = <0x0 0x10000>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd6>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 1>;
+ power-domains = <&cpu_pd6>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
l2_1: l2-cache {
compatible = "cache";
@@ -134,9 +127,8 @@ cpu7: cpu@10100 {
reg = <0x0 0x10100>;
enable-method = "psci";
next-level-cache = <&l2_1>;
- power-domains = <&cpu_pd7>;
- power-domain-names = "psci";
- clocks = <&pdp_scmi_perf 1>;
+ power-domains = <&cpu_pd7>, <&scmi_perf 1>;
+ power-domain-names = "psci", "perf";
};
cpu-map {
@@ -235,9 +227,9 @@ scmi: scmi {
#address-cells = <1>;
#size-cells = <0>;
- pdp_scmi_perf: protocol@13 {
+ scmi_perf: protocol@13 {
reg = <0x13>;
- #clock-cells = <1>;
+ #power-domain-cells = <1>;
};
};
};
--
2.53.0
next reply other threads:[~2026-05-08 8:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 8:27 Mukesh Ojha [this message]
2026-05-08 8:44 ` [PATCH] arm64: dts: qcom: kaanapali: Switch SCMI perf protocol to use power-domain-cells Konrad Dybcio
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