From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4CFA3947AB; Fri, 8 May 2026 11:18:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778239097; cv=none; b=CSZ7cWpKCqFW0BJGhYaTKm5hayUvf0mlmMM0Z/7lgq1T5wazA+Jbl+BevvY7Q+HNol7Jgb5XgBCIVd5K14vjDh9cyOkao10AKXpKi8NlzGRjmHbLHCcu5wf/XnlO66Ki0YfeWRmi2AHmK1OT3ahIhdm8+1PeD0yG5lPQiVZbplw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778239097; c=relaxed/simple; bh=LPtr7w2nYOqw8dfCpcpjIbFy+ffK3EbTobMsBuRYFL0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dXATeRP1F9GFux0JpRUKdeyQnQPDOkBtqPKwFS4YE/N48p/KLMI3/yCKxAV6AnzRfSUTudbmIEPWhamQmHW7t9WrqXClZ/NSe4Mj8anwZWSmaKiu9mE7R0+CohwNuhNlq9NzyfG0z7MsxU0KQEe0UyX2FUTvlrlprpq6TtoL5L0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=XZ/8PYWI; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="XZ/8PYWI" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 648BGgTrA3763939, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1778239002; bh=LVbWJ7YEFqXP/wDP8I/Rz74VaCJkb26ggR3PK+98aHY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=XZ/8PYWITbCRCncsUJobgcNRMdWmFBNzOUHYRBnLkIsmaL7q7+nUhCw9QHE6E4lHr tpS7IeqDc7O5h8Uw6YAcL+agnb1taG+uU/2I7oY1hMYEmmeTu5c1TPKdxz77oSuOXT CVZXKNLJ6VSKIr9Wd+W/ee0PIimnrv0vUCkwA3SvTxL7Sscuqh4Q57nNnIKrt0mmzn eCfsxIVdOioRJURYmKh27RtFR3I3X4k1b4oSVFIC54R+O0UdjxBTK9WnRWZaL32Gii iE3uAJKQytaGvVD3ZNczxkJyCiKWlPc5hQGFCNLvL1rcnngFSNMEeFCRcgv7sXs+AH iJcxFwRfQpVNQ== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.27/5.94) with ESMTPS id 648BGgTrA3763939 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 8 May 2026 19:16:42 +0800 Received: from RTKEXHMBS01.realtek.com.tw (172.21.6.40) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 8 May 2026 19:16:42 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS01.realtek.com.tw (172.21.6.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 8 May 2026 19:16:42 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 8 May 2026 19:16:42 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v7 02/10] reset: Add Realtek basic reset support Date: Fri, 8 May 2026 19:16:33 +0800 Message-ID: <20260508111641.3192177-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260508111641.3192177-1-eleanor.lin@realtek.com> References: <20260508111641.3192177-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Cheng-Yu Lee Define the reset operations backed by a regmap-based register interface and prepare the reset controller to be registered through the reset framework. Since the reset controllers on Realtek SoCs often share the same register space with the clock controllers, this common framework is designed to extract the regmap and device tree node from the parent device (e.g., an auxiliary device parent). Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- MAINTAINERS | 1 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 8 +++ drivers/reset/realtek/Makefile | 2 + drivers/reset/realtek/common.c | 90 ++++++++++++++++++++++++++++++++++ drivers/reset/realtek/common.h | 29 +++++++++++ 7 files changed, 132 insertions(+) create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/common.c create mode 100644 drivers/reset/realtek/common.h diff --git a/MAINTAINERS b/MAINTAINERS index 4af7515664f8..ff0347f6556d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22434,6 +22434,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* F: include/dt-bindings/reset/realtek* diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..45a4227b5f44 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -418,6 +418,7 @@ config RESET_ZYNQMP source "drivers/reset/amlogic/Kconfig" source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/realtek/Kconfig" source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..7330fee91365 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y += core.o obj-y += amlogic/ obj-y += hisilicon/ +obj-y += realtek/ obj-y += spacemit/ obj-y += starfive/ obj-y += sti/ diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig new file mode 100644 index 000000000000..bb6dd856a64a --- /dev/null +++ b/drivers/reset/realtek/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config RESET_RTK_COMMON + tristate "Realtek common reset driver" if COMPILE_TEST + help + This option enables the common reset controller library for + Realtek SoCs. It provides shared reset control operations + (assert, deassert, status) and a registration helper function + that other Realtek-specific reset drivers can use. diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile new file mode 100644 index 000000000000..b59a3f7f2453 --- /dev/null +++ b/drivers/reset/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RESET_RTK_COMMON) += common.o diff --git a/drivers/reset/realtek/common.c b/drivers/reset/realtek/common.c new file mode 100644 index 000000000000..2ce20c25377b --- /dev/null +++ b/drivers/reset/realtek/common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include +#include "common.h" + +static inline struct rtk_reset_data *to_rtk_reset_controller(struct reset_controller_dev *r) +{ + return container_of(r, struct rtk_reset_data, rcdev); +} + +static inline const struct rtk_reset_desc *rtk_reset_get_desc(struct rtk_reset_data *data, + unsigned long idx) +{ + return &data->descs[idx]; +} + +static int rtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = desc->write_en ? (0x2U << desc->bit) : 0; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = mask; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_status(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 val; + int ret; + + desc = rtk_reset_get_desc(data, idx); + ret = regmap_read(data->regmap, desc->ofs, &val); + if (ret) + return ret; + + return !((val >> desc->bit) & 1); +} + +static const struct reset_control_ops rtk_reset_ops = { + .assert = rtk_reset_assert, + .deassert = rtk_reset_deassert, + .status = rtk_reset_status, +}; + +/* The caller must initialize data->descs, data->rcdev.nr_resets and + * data->rcdev.owner before calling rtk_reset_controller_add(). + */ +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_data *data) +{ + data->regmap = dev_get_platdata(dev); + data->rcdev.ops = &rtk_reset_ops; + data->rcdev.dev = dev; + data->rcdev.of_node = dev->parent->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} +EXPORT_SYMBOL_NS_GPL(rtk_reset_controller_add, "REALTEK_RESET"); + +MODULE_DESCRIPTION("realtek reset infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/reset/realtek/common.h b/drivers/reset/realtek/common.h new file mode 100644 index 000000000000..42eb41eae2ec --- /dev/null +++ b/drivers/reset/realtek/common.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + * Author: Yu-Chun Lin + */ + +#ifndef __RESET_REALTEK_COMMON_H +#define __RESET_REALTEK_COMMON_H + +#include + +struct regmap; + +struct rtk_reset_desc { + u32 ofs; + u32 bit; + bool write_en; +}; + +struct rtk_reset_data { + struct reset_controller_dev rcdev; + const struct rtk_reset_desc *descs; + struct regmap *regmap; +}; + +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_data *initdata); + +#endif /* __RESET_REALTEK_COMMON_H */ -- 2.34.1