From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC347382F00; Fri, 8 May 2026 11:23:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778239402; cv=none; b=hG0VdfVh8T8EynF5QF+JTtu4fynTD3ooIbCAgSiJQD34zQxnZFVJgdGTTyfb2d8mfglN0vyspgGCd35qnO/Z8C33JMaz4MSfpEEJ5WwhJbkAMg+4LDtc3YKAsWFOH5obXlTvM8cfpJaKwFF2o8JUXaj29GU0f9SPANc3lkhR1LM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778239402; c=relaxed/simple; bh=BCIW8buEqE5jd6zwfLPqWshQHwruVnljujWd3gOftvw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=VSNoOTfXSKZ7bjK8Vcj8MkZbcY3NcgkctDZBxYVFe2zMfEyQLYZH1kFBvHa9TCtCzq+f+hAsM5fh87pgrGvXvC3AiguEg3s4s04UfP/WuEmth84T6tS8TMwRELul6XB90V5Pospk04eHzu4nlliy0svb5kUdoMC8sSnqaDB+y54= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=rxOPa2rV; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="rxOPa2rV" Received: from killaraus.ideasonboard.com (2001-14ba-70f3-e800--a06.rev.dnainternet.fi [IPv6:2001:14ba:70f3:e800::a06]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 15272BCA; Fri, 8 May 2026 13:23:11 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1778239391; bh=BCIW8buEqE5jd6zwfLPqWshQHwruVnljujWd3gOftvw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=rxOPa2rVxyMWrzHoMeqqFuvpuqSX3x5Qt9NNkBjO41TQ60+sW1kSBotfz+bBZoMnS JEv29K0XrRxrcTwtgI6H/9RblMeMa5wjCEPuN1ZrHwFAX0IrtzhooghME6SiikRXfe X0QZTXdod/CS6psXGWfJZtmBgC+99vd3hWkKdxaM= Date: Fri, 8 May 2026 14:23:14 +0300 From: Laurent Pinchart To: "Lad, Prabhakar" Cc: Biju Das , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Tommaso Merciai , Lad Prabhakar Subject: Re: [PATCH 3/4] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits Message-ID: <20260508112314.GF2176058@killaraus.ideasonboard.com> References: <20260429170012.366537-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260429170012.366537-4-prabhakar.mahadev-lad.rj@bp.renesas.com> <20260506201400.GC1652535@killaraus.ideasonboard.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, May 08, 2026 at 11:00:15AM +0100, Lad, Prabhakar wrote: > On Wed, May 6, 2026 at 9:14 PM Laurent Pinchart wrote: > > On Wed, Apr 29, 2026 at 06:00:11PM +0100, Prabhakar wrote: > > > From: Lad Prabhakar > > > > > > Move pixel clock validation from a fixed encoder check to per SoC > > > constraints stored in rzg2l_du_device_info. > > > > > > Pixel clock limits differ across SoCs in the RZ DU family and cannot be > > > expressed by a single shared rule. For example, RZ/G2UL (R9A07G043U) > > > limits the DPAD0 pixel clock to 83.5 MHz, while other SoCs such as > > > RZ/T2H require a wider operating range. > > > > > > Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to > > > describe the supported pixel clock range for each SoC. Update > > > rzg2l_du_encoder_mode_valid() to return MODE_CLOCK_LOW when the pixel > > > clock falls below mode_clock_min and MODE_CLOCK_HIGH when it exceeds > > > mode_clock_max. > > > > > > Set the pixel clock limits for RZ/G2UL(R9A07G043U) to 20.875MHz minimum > > > and 83.5MHz maximum. > > > > > > Signed-off-by: Lad Prabhakar > > > --- > > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 2 ++ > > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++ > > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 6 +++++- > > > drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h | 2 ++ > > > 4 files changed, 13 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > > > index 0fef33a5a089..3b7162c6e1f4 100644 > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c > > > @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = { > > > .port = 0, > > > }, > > > }, > > > + .mode_clock_min = 20875, > > > + .mode_clock_max = 83500, > > > }; > > > > > > static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > > index 58806c2a8f2b..885558eb9547 100644 > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h > > > @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing { > > > * struct rzg2l_du_device_info - DU model-specific information > > > * @channels_mask: bit mask of available DU channels > > > * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*) > > > + * @mode_clock_min: minimum pixel clock in kHz > > > + * @mode_clock_max: maximum pixel clock in kHz > > > */ > > > struct rzg2l_du_device_info { > > > unsigned int channels_mask; > > > struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; > > > + u32 mode_clock_min; > > > + u32 mode_clock_max; > > > }; > > > > > > #define RZG2L_DU_MAX_CRTCS 1 > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > > > index d53068733c66..ad02efec1c23 100644 > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c > > > @@ -50,8 +50,11 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder, > > > const struct drm_display_mode *mode) > > > { > > > struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder); > > > + const struct rzg2l_du_device_info *info = renc->info; > > > > You could use > > > > struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev); > > const struct rzg2l_du_device_info *info = rcdu->info; > > > > and avoid the info pointer in struct rzg2l_du_encoder. Up to you. > > Agreed, I will drop the info pointer for now. > > > > > > > - if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500) > > > + if (info->mode_clock_min && mode->clock < info->mode_clock_min) > > > + return MODE_CLOCK_LOW; > > > + if (info->mode_clock_max && mode->clock > info->mode_clock_max) > > > return MODE_CLOCK_HIGH; > > > > The new check now applies to all outputs, not just the DPAD0 output. Is > > that intentional ? > > The RZ/G2UL SoC only supports DPAD0 so the check is redundant. Ah right. Please mention that in the commit message. > > > > > > return MODE_OK; > > > @@ -107,6 +110,7 @@ int rzg2l_du_encoder_init(struct rzg2l_du_device *rcdu, > > > if (IS_ERR(renc)) > > > return PTR_ERR(renc); > > > > > > + renc->info = rcdu->info; > > > renc->output = output; > > > drm_encoder_helper_add(&renc->base, &rzg2l_du_encoder_helper_funcs); > > > > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h > > > index 3e430c1f6132..39a1d178b856 100644 > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.h > > > @@ -14,10 +14,12 @@ > > > #include > > > > > > struct rzg2l_du_device; > > > +struct rzg2l_du_device_info; > > > > > > struct rzg2l_du_encoder { > > > struct drm_encoder base; > > > enum rzg2l_du_output output; > > > + const struct rzg2l_du_device_info *info; > > > > If you want to keep a pointer here to avoid going through > > to_rzg2l_du_device(), I would store a backpointer to rzg2l_du_device > > instead of just an info pointer, it could come handy in other places. > > As agreed above I will drop this pointer for now. -- Regards, Laurent Pinchart