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[46.150.62.216]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-454913049ecsm13254407f8f.19.2026.05.09.12.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 May 2026 12:00:22 -0700 (PDT) From: Jernej Skrabec X-Google-Original-From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, jernej.skrabec@gmail.com Subject: [PATCH v2 2/8] clk: sunxi-ng: de2: Export register regmap for DE33 Date: Sat, 9 May 2026 21:00:09 +0200 Message-ID: <20260509190015.79086-3-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260509190015.79086-1-jernej.skrabec@siol.net> References: <20260509190015.79086-1-jernej.skrabec@siol.net> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Jernej Skrabec DE33 clock pre-set plane mapping, which is not something that we want from clock driver. Export registers instead, so DRM driver can set them properly. Signed-off-by: Jernej Skrabec --- Changes from v1: - used access tables instead of functions - used macro for max register - used dev_of_node() instead of open coding drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 48 ++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 6ec6c0dc4c26..26d8abd5fac6 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include #include +#include #include #include "ccu_common.h" @@ -283,6 +285,36 @@ static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = { .num_resets = ARRAY_SIZE(sun50i_h616_de33_resets), }; +/* + * Add a regmap for the DE33 plane driver to access plane + * mapping registers. + * Only these registers are allowed to be written, to prevent + * overriding clock and reset configuration. + */ + +#define SUN50I_DE33_CHN2CORE_REG 0x24 +#define SUN50I_DE33_PORT12CHN_REG 0x2c + +static const struct regmap_range sun8i_de2_ccu_regmap_accessible_ranges[] = { + regmap_reg_range(SUN50I_DE33_CHN2CORE_REG, SUN50I_DE33_PORT12CHN_REG), +}; + +static const struct regmap_access_table sun8i_de2_ccu_regmap_accessible_table = { + .yes_ranges = sun8i_de2_ccu_regmap_accessible_ranges, + .n_yes_ranges = ARRAY_SIZE(sun8i_de2_ccu_regmap_accessible_ranges), +}; + +static const struct regmap_config sun8i_de2_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = SUN50I_DE33_PORT12CHN_REG, + + /* other devices have no business accessing other registers */ + .wr_table = &sun8i_de2_ccu_regmap_accessible_table, + .rd_table = &sun8i_de2_ccu_regmap_accessible_table, +}; + static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct clk *bus_clk, *mod_clk; @@ -336,13 +368,23 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) } /* - * The DE33 requires these additional (unknown) registers set + * The DE33 requires these additional plane mapping registers set * during initialisation. */ if (of_device_is_compatible(pdev->dev.of_node, "allwinner,sun50i-h616-de33-clk")) { - writel(0, reg + 0x24); - writel(0x0000a980, reg + 0x28); + struct regmap *regmap; + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun8i_de2_ccu_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + goto err_assert_reset; + } + + ret = of_syscon_register_regmap(dev_of_node(&pdev->dev), regmap); + if (ret) + goto err_assert_reset; } ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); -- 2.54.0