[PATCH] dt-bindings: misc: add documentation for Xilinx AXI-Stream FIFO IP core

[Kartik Nair <contact.kartikn@gmail.com>]

Add device tree binding documentation for the Xilinx AXI-Stream FIFO
IP core (PG080). This documents the compatible strings used in
drivers/staging/axis-fifo/axis-fifo.c which were previously flagged
as undocumented by checkpatch.

Documented compatible strings:
- xlnx,axi-fifo-mm-s-4.1
- xlnx,axi-fifo-mm-s-4.2
- xlnx,axi-fifo-mm-s-4.3

Signed-off-by: Kartik Nair <contact.kartikn@gmail.com>
---
 .../bindings/misc/xlnx,axi-fifo-mm-s.yaml     | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml

diff --git a/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
new file mode 100644
index 000000000..597699034
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx AXI-Stream FIFO IP Core
+
+maintainers:
+  - Jacob Feder <jacobsfeder@gmail.com>
+
+description:
+  The Xilinx AXI-Stream FIFO IP core allows memory-mapped access to an
+  AXI-Stream interface. It supports both transmit and receive FIFO
+  operations via a memory-mapped register interface. See Xilinx PG080
+  for full IP details.
+
+properties:
+  compatible:
+    enum:
+      - xlnx,axi-fifo-mm-s-4.1
+      - xlnx,axi-fifo-mm-s-4.2
+      - xlnx,axi-fifo-mm-s-4.3
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    axi_fifo: fifo@43c00000 {
+        compatible = "xlnx,axi-fifo-mm-s-4.1";
+        reg = <0x43c00000 0x10000>;
+        interrupts = <0 58 4>;
+    };
-- 
2.50.0