From: Yixun Lan <dlan@kernel.org>
To: Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Inochi Amaoto <inochiama@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, spacemit@lists.linux.dev,
linux-kernel@vger.kernel.org, Yixun Lan <dlan@kernel.org>
Subject: [PATCH v2 4/4] clk: spacemit: k3: Add PCIe DBI clock
Date: Mon, 11 May 2026 02:59:12 +0000 [thread overview]
Message-ID: <20260511-06-pci-clk-fix-v2-4-c9a5e563bab3@kernel.org> (raw)
In-Reply-To: <20260511-06-pci-clk-fix-v2-0-c9a5e563bab3@kernel.org>
Add PCIe DBI (Data Bus Interface) clock which was missing, This will
support PCIe driver to explicitly request and enable all clocks that
needed.
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
index 8f0b743046ab..196d32194125 100644
--- a/drivers/clk/spacemit/ccu-k3.c
+++ b/drivers/clk/spacemit/ccu-k3.c
@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT
CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
+CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0);
CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
+CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0);
CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
+CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0);
CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
+CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0);
CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
+CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0);
static const struct clk_parent_data emac_1588_parents[] = {
CCU_PARENT_NAME(vctcxo_24m),
@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
[CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw,
[CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw,
[CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw,
[CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw,
--
2.54.0
prev parent reply other threads:[~2026-05-11 2:59 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 2:59 [PATCH v2 0/4] riscv: spacemit: k3: some clock fixes related to PCIe Yixun Lan
2026-05-11 2:59 ` [PATCH v2 1/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Yixun Lan
2026-05-11 2:59 ` [PATCH v2 2/4] clk: spacemit: k3: Fix PCIe clock register offset Yixun Lan
2026-05-11 2:59 ` [PATCH v2 3/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Yixun Lan
2026-05-11 2:59 ` Yixun Lan [this message]
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