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Mon, 11 May 2026 03:15:49 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-367d628474dsm7257148a91.8.2026.05.11.03.15.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 03:15:49 -0700 (PDT) From: Taniya Das Date: Mon, 11 May 2026 15:45:43 +0530 Subject: [PATCH v4] arm64: dts: qcom: sm8750: Add camera clock controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260511-sm8750_camcc_dt-v4-1-eab4b6c3eaea@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAE6sAWoC/3XP3wqCMBQG8FeRXTfZf1dXvUeErO2Yg3TlTArx3 ZtCEJg3B74D3+9wRhSh8xDRIRtRB4OPPrQpiF2GbG3aK2DvUkaMMEkZ4Tg2upCktKaxtnQ95pI Y7RgteKFQat07qPxrEU/nlGsf+9C9lwMDnbfb1kAxxYJqUBIICNDHEGP+eJqbDU2Tp4FmcmBfR hHGyJphiQFxKSpTcaml2GD4LyPXDE+MoXvH03OGKvKHmabpA55GJvxDAQAA X-Change-ID: 20251203-sm8750_camcc_dt-350a8d217376 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=GfgnWwXL c=1 sm=1 tr=0 ts=6a01ac57 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=YRkI6OSQ6ZkYtCvnlTgA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: KC70_f7GCSrO2gvjlr-XFf4OSAwgqsYj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTExMDExMyBTYWx0ZWRfX/ekQgm+0lhgd KTdsMM8NGnmn/QVvsbvdN+2h11ewg7r2yrBuS/B47tgLLkBpqyO9V97DqZR7cGL5AbxxZwvsD8G IGd/zY5mt3msIhSsx9PDHRxHekaMQd1uYt2EnGIZdepbdximruTje3UEnrxpVFHKrFV2j+Ais0k z7tL0ilHrXphk8yvue7jgnmOuflSkPckjqwqmeAb0woO48CgfwsM348M21gFKHtcR30MsZPRY2q uXJ0RxKdLwmqC2rBx9z9/Jq9O+pepc6xPmKmad1tgIW2wKlmy6LWt9XiSVvec/XM8HPXCSxc8X3 6VmcP8+Y+CDNI0ZWCTsnyoMW8ck8goX5XBWm5RDAS2yKiC37nPvAwY1bw7YQSuy/Ucbsi2Ck7nd eOHrHy6vBNemJEFMnXMbwsmiDKt4dcKULqv/LFkRMKdZIFQcGgSw67iHFcjGXgwTGkVJ+qmI1qw Xb6BCajqj1cyWW8aQGA== X-Proofpoint-ORIG-GUID: KC70_f7GCSrO2gvjlr-XFf4OSAwgqsYj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_03,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605110113 The camera clock controller is split into cambistmclk and camcc. The cambist clock controller handles the mclks and the rest of the clocks of camera are part of the camcc clock controller. Add the camcc clock controller device node for SM8750 SoC. Reviewed-by: Abel Vesa Signed-off-by: Taniya Das --- Changes in v4: - Fix Stray space before the ',' in cambistcc node [Konrad] - Link to v3: https://lore.kernel.org/r/20260225-sm8750_camcc_dt-v3-1-a19d3173a160@oss.qualcomm.com Changes in v3: - Update the Mx phandle to use MXC for camcc node as it is a always ON rail and can sustain this usecase. - Link to v2: https://lore.kernel.org/r/20260220-sm8750_camcc_dt-v2-1-e4b7faf35854@oss.qualcomm.com Changes in v2: - Update the MxC phandle to use MX for camcc node. - Add RB tag [Abel Vesa] and update the commit message. - Link to v1: https://lore.kernel.org/r/20251203-sm8750_camcc_dt-v1-1-418e65e0e4e8@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 37 +++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index 3f0b57f428bbb388521c27d9ae96bbef3d62b2e2..dabff4518867df88d8e4cdc233ef6325635b7ae9 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -2,7 +2,8 @@ /* * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ - +#include +#include #include #include #include @@ -2046,6 +2047,23 @@ aggre2_noc: interconnect@1700000 { clocks = <&rpmhcc RPMH_IPA_CLK>; }; + cambistmclkcc: clock-controller@1760000 { + compatible = "qcom,sm8750-cambistmclkcc"; + reg = <0x0 0x1760000 0x0 0x6000>; + clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MX>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mmss_noc: interconnect@1780000 { compatible = "qcom,sm8750-mmss-noc"; reg = <0x0 0x01780000 0x0 0x5b800>; @@ -2740,6 +2758,23 @@ usb_dwc3_ss: endpoint { }; }; + camcc: clock-controller@ade0000 { + compatible = "qcom,sm8750-camcc"; + reg = <0x0 0xade0000 0x0 0x20000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; --- base-commit: 47b7b5e32bb7264b51b89186043e1ada4090b558 change-id: 20251203-sm8750_camcc_dt-350a8d217376 Best regards, -- Taniya Das