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Card power is supplied by a fixed 3.3V regulator and I/O voltage switching between 1.8V and 3.3V is handled by a GPIO-controlled regulator. The SOCDK board enables the controller for SD-only operation in 4-bit bus width with high-speed and SDR104 UHS-I modes at 200 MHz maximum clock. SDHCI capability overrides clear the SDR50 tuning flag and override the clock base mask to report 200 MHz. Signed-off-by: Tanmay Kathpalia --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 38 +++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 26 +++++++++++++ 2 files changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 352c96d144a8..7e080f13166f 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -300,6 +300,44 @@ portb: gpio-controller@0 { }; }; + sd_emmc_power: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-name = "card-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sd_io_1v8_reg: regulator-1p8v { + compatible = "regulator-gpio"; + regulator-name = "sd-bus-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + emmc: mmc@10808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,agilex5-sd6hc", "cdns,sd6hc"; + reg = <0x10808000 0x1000>; + interrupts = ; + fifo-depth = <0x800>; + resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>; + reset-names = "sdhc-reset", "combophy", "sdmmc-ocp"; + /* + * "ciu" (SDMCLK) is listed first so it is selected as the + * primary clock by the SDHCI platform layer; the SD6HC PHY + * timing calculations are derived from this clock rate. + */ + clocks = <&clkmgr AGILEX5_SDMCLK>, <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "ciu", "biu"; + iommus = <&smmu 5>; + dma-coherent; + status = "disabled"; + }; + nand: nand-controller@10b80000 { compatible = "cdns,hp-nfc"; reg = <0x10b80000 0x10000>, diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index 262bb3e8e5c7..a9de824e292a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -98,6 +98,32 @@ root: partition@4200000 { }; }; +&sd_io_1v8_reg { + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; +}; + +&emmc { + status = "okay"; + + no-mmc; + disable-wp; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr104; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + /* + * SDHCI capability overrides: + * - caps_mask[0] 0x0000ff00 / caps[0] 0x0000c800: + * Override SDHCI_CLOCK_BASE_MASK to 0xc8 (200 MHz). + * - caps_mask[1] 0x00002000 / caps[1] 0: + * Clear SDHCI_USE_SDR50_TUNING; SDR50 tuning is unsupported. + */ + sdhci-caps = <0x00000000 0x0000c800>; + sdhci-caps-mask = <0x00002000 0x0000ff00>; +}; + &uart0 { status = "okay"; }; -- 2.43.7