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Update the SoC dtsi with a fixed 1.8V regulator for eMMC I/O voltage. Add socfpga_agilex5_socdk_emmc.dts with eMMC controller configured for: - 8-bit bus width - Non-removable eMMC device - High-speed, HS200, and HS400 modes at 1.8V - 200MHz maximum frequency with SDHCI clock base capability override Signed-off-by: Tanmay Kathpalia --- arch/arm64/boot/dts/intel/Makefile | 1 + .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 8 ++ .../dts/intel/socfpga_agilex5_socdk_emmc.dts | 111 ++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 33fcc55d0cb9..5bbbcfda1f48 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -8,5 +8,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex5_socdk_emmc.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 7e080f13166f..feb4ccb317a7 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -317,6 +317,14 @@ sd_io_1v8_reg: regulator-1p8v { <3300000 0x0>; }; + emmc_io_1v8_reg: regulator-fixed-1p8v { + compatible = "regulator-fixed"; + regulator-name = "emmc-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + emmc: mmc@10808000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts new file mode 100644 index 000000000000..87bde9fa69c6 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK eMMC daughter board"; + compatible = "intel,socfpga-agilex5-socdk-emmc", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&porta 6 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&porta 7 GPIO_ACTIVE_HIGH>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac0_phy0>; + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i3c0 { + status = "okay"; +}; + +&i3c1 { + status = "okay"; +}; + +&emmc { + status = "okay"; + + no-sd; + no-sdio; + no-1-8-v; + disable-wp; + non-removable; + cap-mmc-highspeed; + mmc-hs400-1_8v; + mmc-hs200-1_8v; + bus-width = <8>; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&emmc_io_1v8_reg>; + max-frequency = <200000000>; + /* + * SDHCI capability overrides: + * - caps_mask[0] 0x0000ff00 / caps[0] 0x0000c800: + * Override SDHCI_CLOCK_BASE_MASK to 0xc8 (200 MHz). + */ + sdhci-caps = <0x00000000 0x0000c800>; + sdhci-caps-mask = <0x00000000 0x0000ff00>; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- 2.43.7