From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD69637F72A for ; Mon, 11 May 2026 21:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778535642; cv=none; b=FVIIVAp7o5v1cWV7otZcxZWIVakkJ8myMVMufcyjyt8YJN40GT3O2pxY7iOBZs+QqVq6/a7qD/LTdFS30BrEN99mRZ7omEbo4QJedAgGQqp4mG/j99T4BxzzpXvpXuDN9AIAW+GyksM57v6OMzcwqoOehQKZrYidvBXo2KwXIOo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778535642; c=relaxed/simple; bh=3LzAofv+LQG9Fp0qbhC3qAsGygIC5tOH4m2QX7t2GEg=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=S1aADPEPWTBZ3V3LN/+Uy9+49CVWrcYv8RrOqN+ucqgSvDAl3iYbGChcQ5nmDRzZ9a/52l0xyez1bMWIXjCXRzuDmYUIQAZWpSnHw5ah8QIFtIdD/Q0P1tQtkm48IUpsFzfAZ4wHoUdBjvA/5cZ169izikykj8RP5Q++RxdPn1M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IjyHzPZg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IjyHzPZg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BEA9C2BCB0; Mon, 11 May 2026 21:40:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778535642; bh=3LzAofv+LQG9Fp0qbhC3qAsGygIC5tOH4m2QX7t2GEg=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From; b=IjyHzPZgiQv1jIzVte30CUPfUT8K/EiZlCeIE/SZjZPPXzAAKp79D2uYMbUaE5buc Zq3VDSyWGAjpTuuB53/++D4MVdAgfjYpnMI4uRde5mUDJxL3yZUPB/+t8lYLuobfa9 GrFuUirBngoNtitQnv4RLBxCpMgOEtWgik8idFFzaB68vqlDNFoDPYiKI7/TyQw17o 3iWlncdU1UZQRWS7rUF4GgLzAYEMKzSGV9XZTahzv3t5w1jsLOlTEVd9b5W+kqgHJO thuo62NTE3gDxG/LfKpHQqKwkH5pEBVgQDWoXLHNgrgfyPjR+MJgjDxJL+YGTA2HTV Ewk01CLFVcwrg== From: sashiko-bot@kernel.org Subject: Re: [PATCH RFC 1/4] dt-bindings: clk: zte: Add zx297520v3 clock and reset bindings. Reply-To: sashiko@lists.linux.dev To: =?utf-8?b?U3RlZmFuIETDtnNpbmdlcg==?= Cc: krzk+dt@kernel.org, conor+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org In-Reply-To: <20260510-zx29clk-v1-1-e1bacfffe967@gmail.com> References: <20260510-zx29clk-v1-1-e1bacfffe967@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Mon, 11 May 2026 21:40:41 +0000 Message-Id: <20260511214042.5BEA9C2BCB0@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 3 potential issue(= s) to consider: - [Medium] Incomplete Device Tree modeling and schema validation for the ma= trix clock controller. - [Low] The 'osc26m' and 'osc32k' fixed-clock example nodes are missing the= mandatory 'clock-frequency' property. - [Low] Non-standard generic node names in schema examples. -- commit 241b89034c405c46e2b45636517463ab2381b279 Author: Stefan D=C3=B6singer dt-bindings: clk: zte: Add zx297520v3 clock and reset bindings. This commit introduces device tree bindings for the ZTE zx297520v3 clock and reset controllers. It defines compatible strings for the top, matrix, and lsp controllers, along with required properties and standard macros. > diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-clk.y= aml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-clk.yaml > new file mode 100644 > index 0000000000000..3b7084a18a975 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-clk.yaml [ ... ] > + The matrix controller consumes clocks generated by PLLs in the top > + controller, but there are no controls in the top controller to sever t= his > + link. The interface between these controllers is not expressed in the = device > + tree, but the matrix controller cannot work without the clock handles > + registered by the top controller. Should this hardware dependency be explicitly modeled in the device tree? Device tree design principles generally rely on explicitly modeled connections to handle probe ordering correctly. [ ... ] > +properties: > + compatible: > + enum: > + - zte,zx297520v3-topclk > + - zte,zx297520v3-matrixclk > + - zte,zx297520v3-lspclk > + > + clocks: > + minItems: 2 > + maxItems: 10 > + > + clock-names: > + minItems: 2 > + maxItems: 10 [ ... ] > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: zte,zx297520v3-topclk [ ... ] > + - if: > + properties: > + compatible: > + contains: > + const: zte,zx297520v3-lspclk Since clocks and clock-names are defined globally in the schema, but there is no conditional block explicitly forbidding them for the matrix controller using zte,zx297520v3-matrixclk, will the schema silently permit invalid clo= ck assignments for the matrix node? Could an if/then block be added to set clocks to false for the matrix controller? [ ... ] > +examples: > + - | > + #include > + > + osc26m: osc26m { > + compatible =3D "fixed-clock"; > + clock-output-names =3D "osc26m"; > + #clock-cells =3D <0>; > + }; > + > + osc32k: osc32k { > + compatible =3D "fixed-clock"; > + clock-output-names =3D "osc32k"; > + #clock-cells =3D <0>; > + }; Are these fixed-clock example nodes missing the mandatory clock-frequency property? Omitting it might cause dt_binding_check to report schema validation errors. > + > + topclk: topclk@13b000 { > + compatible =3D "zte,zx297520v3-topclk"; [ ... ] > + matrixclk: matrixclk@1306000 { > + compatible =3D "zte,zx297520v3-matrixclk"; [ ... ] > + lspclk: lspclk@1400000 { > + compatible =3D "zte,zx297520v3-lspclk"; This isn't a bug, but should these node names reflect the generic class of the device, like clock-controller@13b000, instead of hardware block designations like topclk, matrixclk, and lspclk? Standard conventions require generic node names, and dt_binding_check might warn about this. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260510-zx29clk-v1= -0-e1bacfffe967@gmail.com?part=3D1