From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58136394E96; Tue, 12 May 2026 13:27:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778592469; cv=none; b=sYAHoy+v7BKgnxeXOj0q2e7f/jUFy47aCmSGO8MIykyc73jb/RZKNoFg7LA7ANLAIcDeOEY2NPAgb+mSMf3SK59AzkJJ31mwsq9P10crYT0TKBiA3z4Ms0EepfWb17Ig+xBfrO2/PiCWQrP1vKbfsPgTQDYMh9eZCkx17bshVNQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778592469; c=relaxed/simple; bh=4PGyunDk+6rrkKYAnv/ZSQthdzJY/qCFG5my7ZKgApM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mTKZOC5OGhxtmzzeieQwm+rikZqI6X75jlOwrCQehylwzIKnaljqDWywh0uztV4KHBiGZIwJquTc/PlhJ645Mjb+QAWP/GZaoGZjRxJDOFaXWssFMwKFLBHi5P2BrXJIwAE7JEHV3tu+QXZu6eNbdUfFgrptjjlf2Z5RPWbJgS4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=SIV9LACv; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="SIV9LACv" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 03D284E42C8A; Tue, 12 May 2026 13:27:47 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id CC88C60646; Tue, 12 May 2026 13:27:46 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 7A44E11AF8C7F; Tue, 12 May 2026 15:27:44 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1778592466; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=nfzwc68iBSisSrkThM7+r8IbLM44eOfIaoNviBc37GY=; b=SIV9LACv40NsZe5DTDchW2r5pIbcnAFMHw5JYXy4NQUDg56fwvolxqn3R4cFmB99v45RcA HgyxG/G75SaSlHg2sXK/oXQhd/uS17IL1uBPCPSBekyY3dlS3RBroz1Z90nmthLHiM5osq lttBloQV9kRpHOuS6OdZLQbAbc3Ou05/LN+znznzqXfBCFKVEX0K+lYH5Jj1JufqCBgG30 Ta84pE0rl+BJfCWRVlz886R1EzYvTVNotMA+MtnWTWt4lA8qLSjK+p91dyorGhHClTqyjJ +TDuDxDQnY5rzrBQJ4kichFABQVXY/hSLjJcDfnVteO420vOhH+94XJRM8w9oA== From: =?utf-8?q?Beno=C3=AEt_Monin?= Date: Tue, 12 May 2026 15:27:04 +0200 Subject: [PATCH v6 5/9] clk: eyeq: Prefix the PLL registers with the PLL type Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260512-clk-eyeq7-v6-5-0540cce18fb2@bootlin.com> References: <20260512-clk-eyeq7-v6-0-0540cce18fb2@bootlin.com> In-Reply-To: <20260512-clk-eyeq7-v6-0-0540cce18fb2@bootlin.com> To: Vladimir Kondratiev , Gregory CLEMENT , =?utf-8?q?Th=C3=A9o_Lebrun?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel Cc: =?utf-8?q?Beno=C3=AEt_Monin?= , Thomas Petazzoni , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Rename the PLL registers to make room for other PLL types that are present in the eyeQ7H. Move the access to the PLL register inside the function parsing it as both call sites were doing the same thing. Signed-off-by: Benoît Monin --- drivers/clk/clk-eyeq.c | 76 +++++++++++++++++++++++--------------------------- 1 file changed, 35 insertions(+), 41 deletions(-) diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c index d9303c2c7aa5..e4e690a12a23 100644 --- a/drivers/clk/clk-eyeq.c +++ b/drivers/clk/clk-eyeq.c @@ -48,28 +48,28 @@ #include /* In frac mode, it enables fractional noise canceling DAC. Else, no function. */ -#define PCSR0_DAC_EN BIT(0) +#define FRACG_PCSR0_DAC_EN BIT(0) /* Fractional or integer mode */ -#define PCSR0_DSM_EN BIT(1) -#define PCSR0_PLL_EN BIT(2) +#define FRACG_PCSR0_DSM_EN BIT(1) +#define FRACG_PCSR0_PLL_EN BIT(2) /* All clocks output held at 0 */ -#define PCSR0_FOUTPOSTDIV_EN BIT(3) -#define PCSR0_POST_DIV1 GENMASK(6, 4) -#define PCSR0_POST_DIV2 GENMASK(9, 7) -#define PCSR0_REF_DIV GENMASK(15, 10) -#define PCSR0_INTIN GENMASK(27, 16) -#define PCSR0_BYPASS BIT(28) +#define FRACG_PCSR0_FOUTPOSTDIV_EN BIT(3) +#define FRACG_PCSR0_POST_DIV1 GENMASK(6, 4) +#define FRACG_PCSR0_POST_DIV2 GENMASK(9, 7) +#define FRACG_PCSR0_REF_DIV GENMASK(15, 10) +#define FRACG_PCSR0_INTIN GENMASK(27, 16) +#define FRACG_PCSR0_BYPASS BIT(28) /* Bits 30..29 are reserved */ -#define PCSR0_PLL_LOCKED BIT(31) +#define FRACG_PCSR0_PLL_LOCKED BIT(31) -#define PCSR1_RESET BIT(0) -#define PCSR1_SSGC_DIV GENMASK(4, 1) +#define FRACG_PCSR1_RESET BIT(0) +#define FRACG_PCSR1_SSGC_DIV GENMASK(4, 1) /* Spread amplitude (% = 0.1 * SPREAD[4:0]) */ -#define PCSR1_SPREAD GENMASK(9, 5) -#define PCSR1_DIS_SSCG BIT(10) +#define FRACG_PCSR1_SPREAD GENMASK(9, 5) +#define FRACG_PCSR1_DIS_SSCG BIT(10) /* Down-spread or center-spread */ -#define PCSR1_DOWN_SPREAD BIT(11) -#define PCSR1_FRAC_IN GENMASK(31, 12) +#define FRACG_PCSR1_DOWN_SPREAD BIT(11) +#define FRACG_PCSR1_FRAC_IN GENMASK(31, 12) struct eqc_pll { unsigned int index; @@ -162,34 +162,40 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div) *div >>= shift; } -static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, - unsigned long *div, unsigned long *acc) +static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult, + unsigned long *div, unsigned long *acc) { unsigned long spread; + u32 r0, r1; + u64 val; - if (r0 & PCSR0_BYPASS) { + val = readq(base); + r0 = val; + r1 = val >> 32; + + if (r0 & FRACG_PCSR0_BYPASS) { *mult = 1; *div = 1; *acc = 0; return 0; } - if (!(r0 & PCSR0_PLL_LOCKED)) + if (!(r0 & FRACG_PCSR0_PLL_LOCKED)) return -EINVAL; - *mult = FIELD_GET(PCSR0_INTIN, r0); - *div = FIELD_GET(PCSR0_REF_DIV, r0); + *mult = FIELD_GET(FRACG_PCSR0_INTIN, r0); + *div = FIELD_GET(FRACG_PCSR0_REF_DIV, r0); /* Fractional mode, in 2^20 (0x100000) parts. */ - if (r0 & PCSR0_DSM_EN) { + if (r0 & FRACG_PCSR0_DSM_EN) { *div *= (1ULL << 20); - *mult = *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1); + *mult = *mult * (1ULL << 20) + FIELD_GET(FRACG_PCSR1_FRAC_IN, r1); } if (!*mult || !*div) return -EINVAL; - if (r1 & (PCSR1_RESET | PCSR1_DIS_SSCG)) { + if (r1 & (FRACG_PCSR1_RESET | FRACG_PCSR1_DIS_SSCG)) { *acc = 0; return 0; } @@ -204,10 +210,10 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, * * Care is taken to avoid overflowing or losing precision. */ - spread = FIELD_GET(PCSR1_SPREAD, r1); + spread = FIELD_GET(FRACG_PCSR1_SPREAD, r1); *acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2); - if (r1 & PCSR1_DOWN_SPREAD) { + if (r1 & FRACG_PCSR1_DOWN_SPREAD) { /* * Downspreading: the central frequency is half a * spread lower. @@ -232,18 +238,12 @@ static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data const struct eqc_pll *pll; struct clk_hw *hw; unsigned int i; - u32 r0, r1; - u64 val; int ret; for (i = 0; i < data->pll_count; i++) { pll = &data->plls[i]; - val = readq(base + pll->reg64); - r0 = val; - r1 = val >> 32; - - ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc); + ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc); if (ret) { dev_warn(dev, "failed parsing state of %s\n", pll->name); cells->hws[pll->index] = ERR_PTR(ret); @@ -799,14 +799,8 @@ static void __init eqc_early_init(struct device_node *np, const struct eqc_pll *pll = &early_data->early_plls[i]; unsigned long mult, div, acc; struct clk_hw *hw; - u32 r0, r1; - u64 val; - val = readq(base + pll->reg64); - r0 = val; - r1 = val >> 32; - - ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc); + ret = eqc_pll_parse_fracg(base + pll->reg64, &mult, &div, &acc); if (ret) { pr_err("failed parsing state of %s\n", pll->name); goto err; -- 2.54.0