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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-368b06d6b33sm425701a91.10.2026.05.11.22.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 22:12:55 -0700 (PDT) From: Kathiravan Thirumoorthy Subject: [PATCH v4 0/4] Add minimal boot support for Qualcomm IPQ9650 SoC Date: Tue, 12 May 2026 10:42:46 +0530 Message-Id: <20260512-ipq9650_boot_to_shell-v4-0-1e87c8326e59@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAM62AmoC/3WOyw6CMBBFf4V0bU2fYF35H8YQWkapASptIRrDv 1vUxI1sJrmTO+fMEwXwFgLaZ0/kYbLBuj4FscmQaar+AtjWKSNGWE44J9jeBpVLUmrnYhldGRp oW0ylIqyopdgZg9LtzcPZ3t/c4+mTw6ivYOIC+zY8DGMSxl+tsSE6/3h/M9Fl+xELKlfEE8UEa 16AFoZXtKYHF8J2GKvWuK7bpoEW8MR/MEmKNRhPsJwVgmmhjFL/YPM8vwDXuo6iNQEAAA== X-Change-ID: 20260330-ipq9650_boot_to_shell-159027d548cc To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Krzysztof Kozlowski X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778562771; l=2956; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=XAAdVzRIgG1++KpC6o+mUhQKjjhsFsPBjnBt299X6wI=; b=fTj0XyZnkBpYSSoL1vJXBeZtf/k3d2jspdBJthXb/1BXpIevuliiA/vaMQhvDK9b2cFNcifqZ HOr3XG7BvZRAXlVpZe0NPW/bR6+rgJH/BgqkPcNuo7sYFt06GgjVtRX X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-ORIG-GUID: SXSVNQ8OyRHQWjEFBTO3bg-3ocUVfKG6 X-Authority-Analysis: v=2.4 cv=CeM4Irrl c=1 sm=1 tr=0 ts=6a02b6d9 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=bC-a23v3AAAA:8 a=VwQbUJbxAAAA:8 a=YURS4O9UCPS1-Wi1IM0A:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTEyMDA0NyBTYWx0ZWRfX84aJ1zvktUmQ HxzWxtF1bm5jwCeDhxy2rtZ9tFvFhitDNpU8gETwHndZVFJTMBV59pfGmmWo9z936L08d1wSGLU AfCA0HumGBo5eyk+QCtcvZEkNxz16OhTHJu+KvWomTh7K6S65BpM9cKqBgsvVSmlCc5l7m7xm/A y6KO2TQj406BovWy5toQw0M3vWGqsyQyom2sQCB1zMjT+Vgn4xwrE4cXQwVrpwI0hXeeQt30lMF J8BtywzwhbWtU14kHylgL6H3TV2GWznciUMFo6vgC3dySb3+shydMfx24Gm7rNc3KAAPotzPa6v 1ioaDAr9S2YctYVoS6qAeXStVbAQ7OYSuTrUS4MqsRSaxKBkqOvtPZjwf8KU7ceRFOtWV4qow/1 5MHm4ixnxybWGE08CNCPD58+299lSO4tlJuttDcRHoZd7/t8AT4kJKx2Q7P3Eq3bZSTKQJxDoi6 3Ef6mzACfjgPaJ0+kAg== X-Proofpoint-GUID: SXSVNQ8OyRHQWjEFBTO3bg-3ocUVfKG6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-11_05,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 phishscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 spamscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605120047 Qualcomm IPQ9650 is a networking SoC targeted at routers, gateways, and access points. This change adds minimal support required to boot the IPQ9650 RDP488 board. Compared to earlier IPQ SoCs, IPQ9650 features a heterogeneous CPU configuration with four Cortex-A55 cores and one Cortex-A78 core, a 2 MB shared L3 cache, SMMU support, IPCC, five PCIe Gen3 controllers, an integrated CDSP for task offloading, enhanced PPE capabilities, and DDR5 memory support. More information can be found at the product page: https://docs.qualcomm.com/doc/87-96766-1/87-96766-1_REV_AA_Qualcomm_Dragonwing_NPro_A8_Elite_Platform_Product_Brief.pdf Signed-off-by: Kathiravan Thirumoorthy --- Changes in v4: - Fixed the qcom,tcsr-mutex region size - Link to v3: https://patch.msgid.link/20260507-ipq9650_boot_to_shell-v3-0-62742b49c991@oss.qualcomm.com Changes in v3: - Added \n before the status property - Rebased on next-20260507 - Dropped the REFGEN, PRIMESS clocks from the bindings and the GCC driver since the ownership of these clocks are in discussion. It will be added back if Linux needs to play with those clocks. - Link to v2: https://lore.kernel.org/all/20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com/ Changes in v2: - Collected the R-b tags - Add the ARM64 dependency to the GCC driver and enable it by default to align with Krzysztof's effort to cleanup the defconfig - Updated the GICv3 interrupt-cells to 4 and added the ppi-partitions and hooked up with the PMU instances. - Made the labels to lower case and kept the \n before status property - Dropped the defconfig patch - Link to v1: https://patch.msgid.link/20260415-ipq9650_boot_to_shell-v1-0-b37eb4c3a1d1@oss.qualcomm.com --- Kathiravan Thirumoorthy (4): dt-bindings: clock: add Qualcomm IPQ9650 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC dt-bindings: qcom: add IPQ9650 boards arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support Documentation/devicetree/bindings/arm/qcom.yaml | 5 + .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 + arch/arm64/boot/dts/qcom/ipq9650.dtsi | 377 +++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9650.c | 3445 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 172 + include/dt-bindings/reset/qcom,ipq9650-gcc.h | 215 ++ 10 files changed, 4373 insertions(+) --- base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83 change-id: 20260330-ipq9650_boot_to_shell-159027d548cc Best regards, -- Kathiravan Thirumoorthy