From: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Kathiravan Thirumoorthy
<kathiravan.thirumoorthy@oss.qualcomm.com>
Subject: [PATCH 1/2] arm64: dts: qcom: ipq9650: add the SMMU device
Date: Tue, 12 May 2026 12:34:54 +0530 [thread overview]
Message-ID: <20260512-ipq9650_more_dev_support-v1-1-c4c627351d80@oss.qualcomm.com> (raw)
In-Reply-To: <20260512-ipq9650_more_dev_support-v1-0-c4c627351d80@oss.qualcomm.com>
Add and enable the support for the SMMU500 found in the IPQ9650 SoC.
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/ipq9650.dtsi | 42 +++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi
index 88bc77009ca0..3e7527609591 100644
--- a/arch/arm64/boot/dts/qcom/ipq9650.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi
@@ -364,6 +364,48 @@ frame@f42d000 {
status = "disabled";
};
};
+
+ iommu@15000000 {
+ compatible = "qcom,ipq9650-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x40000>;
+
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ };
};
timer {
--
2.34.1
next prev parent reply other threads:[~2026-05-12 7:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 7:04 [PATCH 0/2] Add the SMMU and the downlod mode support for Qualcomm's IPQ9650 SoC Kathiravan Thirumoorthy
2026-05-12 7:04 ` Kathiravan Thirumoorthy [this message]
2026-05-12 7:04 ` [PATCH 2/2] arm64: dts: qcom: ipq9650: add the download mode support Kathiravan Thirumoorthy
2026-05-12 15:41 ` [PATCH 0/2] Add the SMMU and the downlod mode support for Qualcomm's IPQ9650 SoC Kathiravan Thirumoorthy
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