From: sashiko-bot@kernel.org
To: "Jian Hu via B4 Relay" <devnull+jian.hu.amlogic.com@kernel.org>
Cc: robh@kernel.org, devicetree@vger.kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL clock controller
Date: Tue, 12 May 2026 04:18:19 +0000 [thread overview]
Message-ID: <20260512041820.19BD2C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260511-b4-a9_clk-v1-2-41cb4071b7c9@amlogic.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The schema conditional block for MCLK PLLs fails to enforce the required second clock input, allowing incomplete device tree nodes to pass validation.
--
commit 5fa007b81417dc37662d2d766cd8ecfc23758d15
Author: Jian Hu <jian.hu@amlogic.com>
dt-bindings: clock: Add Amlogic A9 PLL clock controller
This commit adds the PLL clock controller device tree bindings for the
Amlogic A9 SoC family.
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
> new file mode 100644
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
[ ... ]
> + clocks:
> + items:
> + - description: pll input oscillator gate
> + - description: fixed input clock source for mclk_sel_0
> + - description: u3p2pll input clock source for mclk_sel_0 (optional)
> + minItems: 1
> +
> + clock-names:
> + items:
> + - const: in0
> + - const: in1
> + - const: in2
> + minItems: 1
[ ... ]
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - amlogic,a9-mclk0-pll
> + - amlogic,a9-mclk1-pll
> +
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> +
> + clock-names:
> + maxItems: 3
Does this conditional block also need to specify minItems: 2 for the clocks
and clock-names properties?
The global property definition describes the second clock as a fixed input
clock source without the (optional) designation given to the third clock.
Since the global minItems is 1, omitting a stricter minItems constraint
here causes a schema validation regression where an incomplete device tree
node specifying only a single clock for an MCLK PLL will silently pass,
even though it is missing the mandatory second input.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com?part=2
next prev parent reply other threads:[~2026-05-12 4:18 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 12:47 [PATCH 00/10] Add support for A9 family clock controller Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 01/10] dt-bindings: clock: Add Amlogic A9 SCMI " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL " Jian Hu via B4 Relay
2026-05-12 4:18 ` sashiko-bot [this message]
2026-05-11 12:47 ` [PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 04/10] dt-bindings: clock: Add Amlogic A9 AO " Jian Hu via B4 Relay
2026-05-11 12:47 ` [PATCH 05/10] clk: amlogic: PLL l_detect signal supports active-high configuration Jian Hu via B4 Relay
2026-05-11 15:47 ` Brian Masney
2026-05-11 12:47 ` [PATCH 06/10] clk: amlogic: PLL reset signal supports active-low configuration Jian Hu via B4 Relay
2026-05-11 15:21 ` Brian Masney
2026-05-12 4:48 ` sashiko-bot
2026-05-11 12:47 ` [PATCH 07/10] clk: amlogic: Support POWER_OF_TWO for PLL pre-divider Jian Hu via B4 Relay
2026-05-11 15:23 ` Brian Masney
2026-05-11 12:47 ` [PATCH 08/10] clk: amlogic: Add A9 PLL clock controller driver Jian Hu via B4 Relay
2026-05-11 15:36 ` Brian Masney
2026-05-12 5:56 ` sashiko-bot
2026-05-11 12:47 ` [PATCH 09/10] clk: amlogic: Add A9 peripherals " Jian Hu via B4 Relay
2026-05-11 15:42 ` Brian Masney
2026-05-12 6:18 ` sashiko-bot
2026-05-11 12:47 ` [PATCH 10/10] clk: amlogic: Add A9 AO " Jian Hu via B4 Relay
2026-05-11 15:45 ` Brian Masney
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