Re: [PATCH v1 2/2] LRW UART: serial: add driver for the LRW UART

[<liu.qingtao2@zte.com.cn>]

> On Fri, Feb 13, 2026 at 05:33:34PM +0800, LiuQingtao wrote:
> > From: Wenhong Liu <liu.wenhong35@zte.com.cn>
> >
> > This commit introduces a serial driver for the LRW UART controller
> >
> > Key features implemented:
> > - Support for FIFO mode (16-byte depth)
> > - Baud rate configuration
> > - Standard asynchronous communication formats:
> >   * Data bits: 5, 6, 7, 8, 9 bits
> >   * Parity: odd, even, fixed, none
> >   * Stop bits: 1 or 2 bits
> > - Hardware flow control (RTS/CTS)
> > - Multiple interrupt reporting mechanisms
> >
> > Signed-off-by: Wenhong Liu <liu.wenhong35@zte.com.cn>
> > Signed-off-by: Qingtao Liu <liu.qingtao2@zte.com.cn>
> > ---
> >  MAINTAINERS                      |    3 +
> >  drivers/tty/serial/Kconfig       |   33 +
> >  drivers/tty/serial/Makefile      |    1 +
> >  drivers/tty/serial/lrw_uart.c    | 2822 ++++++++++++++++++++++++++++++
>
> This really is a totally new uart?  No relation to any existing devices
> at all?  Why would that be created?
>
> Anyway, this doesn't seem to build properly, how was it tested?

Yes, it`s a new uart for lrx SoC. The lrx SoC with its related docs will be released soon.

The uart TX & RX test environment:
1.Kernel: linux-next, commit 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0(Tue May 5 14:57:23 2026 +0200),
with CONFIG_SERIAL_LRX_UART and SERIAL_LRX_UART_CONSOLE selected.
2.GCC: 14.1.0.
3.SoC: lrx SoC.


> > --- a/include/uapi/linux/serial_core.h
> > +++ b/include/uapi/linux/serial_core.h
> > @@ -231,6 +231,9 @@
> >  /* Sunplus UART */
> >  #define PORT_SUNPLUS    123
> >  
> > +/* LRW UART */
> > +#define PORT_LRW    124
>
> Why is this id needed?
>
> thanks,
>
> greg k-h

Thanks for notice. This id is not needed actually.
According to https://lore.kernel.org/all/20231008001804.889727-1-jcmvbkbc@gmail.com/, the specific type
of the port is not important to the userspace.