From: sashiko-bot@kernel.org
To: "Benoît Monin" <benoit.monin@bootlin.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH v6 3/9] clk: fixed-factor: Rework initialization with parent clocks
Date: Wed, 13 May 2026 22:23:49 +0000 [thread overview]
Message-ID: <20260513222349.7CA4FC19425@smtp.kernel.org> (raw)
In-Reply-To: <20260512-clk-eyeq7-v6-3-0540cce18fb2@bootlin.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] A fixed-factor clock registered with no parent and the CLK_SET_RATE_PARENT flag will cause a NULL pointer dereference.
--
commit c84e53359c0d9461f122802c5a6acb3dc1fc8cf7
Author: Benoît Monin <benoit.monin@bootlin.com>
clk: fixed-factor: Rework initialization with parent clocks
This commit reworks fixed-factor clock initialization to follow the standard
sequence for setting parent details in the init struct. When a fixed-factor
clock is provided without a parent, it now registers with zero parents
instead of relying on a dummy parent data struct with an invalid index.
> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index 850e8b95f3527..359e91441c740 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -124,13 +124,13 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
> init.name = name;
> init.ops = &clk_fixed_factor_ops;
> init.flags = flags;
> - if (parent_name)
> - init.parent_names = &parent_name;
> - else if (parent_hw)
> - init.parent_hws = &parent_hw;
> + init.parent_names = parent_name ? &parent_name : NULL;
> + init.parent_hws = parent_hw ? &parent_hw : NULL;
> + init.parent_data = pdata;
> + if (parent_name || parent_hw || pdata)
> + init.num_parents = 1;
> else
> - init.parent_data = pdata;
> - init.num_parents = 1;
> + init.num_parents = 0;
This problem wasn't introduced by this patch, but does this expose an
issue if a fixed-factor clock is registered with no parent and the
CLK_SET_RATE_PARENT flag?
If num_parents is 0, clk_factor_determine_rate() will evaluate
clk_hw_get_parent(hw), which will return NULL.
This NULL pointer is then passed directly into clk_hw_round_rate(), which
dereferences it via hw->core without any NULL checks.
Should the clock framework protect against this gracefully, similar to how
divider_ro_determine_rate() in clk-divider.c handles it by checking if
!req->best_parent_hw?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260512-clk-eyeq7-v6-0-0540cce18fb2@bootlin.com?part=3
next prev parent reply other threads:[~2026-05-13 22:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 13:26 [PATCH v6 0/9] Add clock and reset support for Mobileye EyeQ7H Benoît Monin
2026-05-12 13:27 ` [PATCH v6 1/9] dt-bindings: soc: mobileye: Add EyeQ7H OLB Benoît Monin
2026-05-12 13:27 ` [PATCH v6 2/9] reset: eyeq: Add EyeQ7H compatibles Benoît Monin
2026-05-13 22:05 ` sashiko-bot
2026-05-12 13:27 ` [PATCH v6 3/9] clk: fixed-factor: Rework initialization with parent clocks Benoît Monin
2026-05-13 22:23 ` sashiko-bot [this message]
2026-05-12 13:27 ` [PATCH v6 4/9] clk: fixed-factor: Export __clk_hw_register_fixed_factor() Benoît Monin
2026-05-12 13:27 ` [PATCH v6 5/9] clk: eyeq: Prefix the PLL registers with the PLL type Benoît Monin
2026-05-12 13:27 ` [PATCH v6 6/9] clk: eyeq: Introduce a generic clock type Benoît Monin
2026-05-13 23:34 ` sashiko-bot
2026-05-12 13:27 ` [PATCH v6 7/9] clk: eyeq: Convert clocks declaration to eqc_clock Benoît Monin
2026-05-12 13:27 ` [PATCH v6 8/9] clk: eyeq: Drop PLL, dividers, and fixed factors structs Benoît Monin
2026-05-12 13:27 ` [PATCH v6 9/9] clk: eyeq: Add EyeQ7H compatibles Benoît Monin
2026-05-14 0:49 ` sashiko-bot
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