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Thu, 14 May 2026 11:12:43 +0000 From: Changhuang Liang To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Paul Walmsley , Albert Ou , Palmer Dabbelt , Alexandre Ghiti , Philipp Zabel , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Lianfeng Ouyang , Changhuang Liang Subject: [PATCH v2 10/22] dt-bindings: pinctrl: Add starfive,jhb100-sys2-pinctrl Date: Thu, 14 May 2026 04:12:06 -0700 Message-Id: <20260514111218.94519-11-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260514111218.94519-1-changhuang.liang@starfivetech.com> References: <20260514111218.94519-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0028.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:2::18) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1139:EE_ X-MS-Office365-Filtering-Correlation-Id: a9c89d04-e36b-45d9-102d-08deb1a9b831 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|7416014|376014|52116014|1800799024|921020|38350700014|3023799003|22082099003|56012099003|18002099003; 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System-2 domain also supports configuring the pin group voltage. Add relevant definitions for power-source configuration. Signed-off-by: Changhuang Liang --- .../pinctrl/starfive,jhb100-sys2-pinctrl.yaml | 173 ++++++++++++++++++ .../pinctrl/starfive,jhb100-pinctrl.h | 44 +++++ 2 files changed, 217 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml new file mode 100644 index 000000000000..3281c9433281 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys2-pinctrl.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-2 Pin Controller + +description: | + Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd. + + The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1, + per2, per2pok, per3, adc0, adc1, emmc, and vga. + This document provides an overview of the "sys2" pinctrl domain. + + The "sys2" domain has a pin controller which provides + - function selection for GPIO pads. + - GPIO pad configuration. + - GPIO interrupt handling. + + In the SYS2 Pin Controller, there are 37 multi-function GPIO_PADs. Each of + them can be multiplexed to different hardware blocks through function + selection. Each iopad has a maximum of up to 4 functions - 0, 1, 2, and 3. + Function 0 is the default function which is the GPIO function. + Function 1, 2, and 3 are the alternate functions or peripheral signals that + can be routed to the iopad. The function selection can be carried out by + writing the function number to the iopad function select register. + + Each iopad is configurable with parameters such as input-enable, internal + pull-up/pull-down bias, drive strength, schmitt trigger, slew rate, input + debounce nanoseconds, power source and drive type (open-drain or push-pull). + +maintainers: + - Alex Soo + +properties: + compatible: + items: + - const: starfive,jhb100-sys2-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + gpio-controller: true + + '#gpio-cells': + const: 3 + + gpio-ranges: true + + gpio-line-names: true + +patternProperties: + '-grp$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available in the domain. Each subnode will list the + pins it needs, and how they should be configured, with regard to + function selection, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate, input debounce nanoseconds, + drive-open-drain, drive-push-pull, power-source and drive-strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + unevaluatedProperties: false + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. + enum: [ gpio, host0_port80, host1_port80, jtag, smbalert, uart ] + + bias-disable: true + + bias-pull-down: + type: boolean + + bias-pull-up: + oneOf: + - type: boolean + - enum: [ 600, 900, 1200, 2000 ] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + drive-open-drain: true + + drive-push-pull: true + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + drive-strength-microamp: + enum: [ 2000, 4000, 8000, 12000 ] + + input-debounce-nanoseconds: + minimum: 0 + maximum: 4294967295 + + input-disable: true + + input-enable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + power-source: + enum: [ 0, 1, 2 ] + + slew-rate: + enum: [ 0, 1 ] + default: 0 + description: | + 0: slow (half frequency) + 1: fast + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl_sys2: pinctrl@13082000 { + compatible = "starfive,jhb100-sys2-pinctrl"; + reg = <0x0 0x13082000 0x0 0x1000>; + interrupts = <59>; + interrupt-controller; + #interrupt-cells = <3>; + gpio-controller; + #gpio-cells = <3>; + gpio-ranges = <&pinctrl_sys2 0 0 0 32>, + <&pinctrl_sys2 1 0 32 5>; + }; + }; diff --git a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h index 30704a5a3418..89d344763540 100644 --- a/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h +++ b/include/dt-bindings/pinctrl/starfive,jhb100-pinctrl.h @@ -38,4 +38,48 @@ #define PADNUM_SYS1_GPIO_A22 6 #define PADNUM_SYS1_GPIO_A23 7 +/* sys2 pad numbers */ +#define PADNUM_SYS2_GPIO_A24 0 +#define PADNUM_SYS2_GPIO_A25 1 +#define PADNUM_SYS2_GPIO_A26 2 +#define PADNUM_SYS2_GPIO_A27 3 +#define PADNUM_SYS2_GPIO_A28 4 +#define PADNUM_SYS2_GPIO_A29 5 +#define PADNUM_SYS2_GPIO_A30 6 +#define PADNUM_SYS2_GPIO_A31 7 +#define PADNUM_SYS2_GPIO_A32 8 +#define PADNUM_SYS2_GPIO_A33 9 +#define PADNUM_SYS2_GPIO_A34 10 +#define PADNUM_SYS2_GPIO_A35 11 +#define PADNUM_SYS2_GPIO_A36 12 +#define PADNUM_SYS2_GPIO_A37 13 +#define PADNUM_SYS2_GPIO_A38 14 +#define PADNUM_SYS2_GPIO_A39 15 +#define PADNUM_SYS2_GPIO_A40 16 +#define PADNUM_SYS2_GPIO_A41 17 +#define PADNUM_SYS2_GPIO_A42 18 +#define PADNUM_SYS2_GPIO_A43 19 +#define PADNUM_SYS2_GPIO_A44 20 +#define PADNUM_SYS2_GPIO_A45 21 +#define PADNUM_SYS2_GPIO_A46 22 +#define PADNUM_SYS2_GPIO_A47 23 +#define PADNUM_SYS2_GPIO_A48 24 +#define PADNUM_SYS2_GPIO_A49 25 +#define PADNUM_SYS2_GPIO_A50 26 +#define PADNUM_SYS2_GPIO_A51 27 +#define PADNUM_SYS2_GPIO_A52 28 +#define PADNUM_SYS2_GPIO_A53 29 +#define PADNUM_SYS2_GPIO_A54 30 +#define PADNUM_SYS2_GPIO_A55 31 +#define PADNUM_SYS2_GPIO_A56 32 +#define PADNUM_SYS2_GPIO_A57 33 +#define PADNUM_SYS2_GPIO_A58 34 +#define PADNUM_SYS2_GPIO_A59 35 +#define PADNUM_SYS2_GPIO_A60 36 + +/* pinctrl hog power-source value */ +#define JHB100_PINVREF_3_3V 0 +#define JHB100_PINVREF_2_5V 1 +#define JHB100_PINVREF_1_8V 2 + #endif -- 2.25.1