From: sashiko-bot@kernel.org
To: "Junhui Liu" <junhui.liu@pigmoral.tech>
Cc: krzk+dt@kernel.org, devicetree@vger.kernel.org, robh@kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH v5 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90
Date: Thu, 14 May 2026 19:48:14 +0000 [thread overview]
Message-ID: <20260514194815.3483CC2BCB3@smtp.kernel.org> (raw)
In-Reply-To: <20260514-dr1v90-cru-v5-5-34f3021aab51@pigmoral.tech>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `can_ext` and `wdt_ext` fixed-clock nodes are missing the mandatory `clock-frequency` property.
--
commit 2b9cd6d4a55b4608470fd48bd92b6cacba368046
Author: Junhui Liu <junhui.liu@pigmoral.tech>
riscv: dts: anlogic: add clocks and CRU for DR1V90
This commit adds clocks and introduces the Clock and Reset unit node
for the Anlogic DR1V90 SoC. It configures a main crystal oscillator
and two optional external clocks for the CAN and WDT modules.
> diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
> index 9fe183f5f5c8d..574c6608aef01 100644
> --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
> +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi
[ ... ]
> @@ -40,6 +43,26 @@ cpu0_intc: interrupt-controller {
> };
> };
>
> + clocks {
> + can_ext: clock-ext-can {
> + compatible = "fixed-clock";
> + clock-output-names = "can_ext";
> + #clock-cells = <0>;
> + };
> +
> + osc: clock-osc {
> + compatible = "fixed-clock";
> + clock-output-names = "osc";
> + #clock-cells = <0>;
> + };
> +
> + wdt_ext: clock-ext-wdt {
> + compatible = "fixed-clock";
> + clock-output-names = "wdt_ext";
> + #clock-cells = <0>;
> + };
Are the can_ext and wdt_ext fixed-clock nodes missing the mandatory
clock-frequency property?
The fixed-clock devicetree binding requires a clock-frequency property.
Without it, the fixed-clock driver fails to read the frequency and returns
-EIO during both of_fixed_clk_setup and platform probe, failing to register
the clock providers.
Because the cru node specifies these clocks as suppliers, the kernel's
fw_devlink mechanism will indefinitely block the CRU driver from probing.
This recursively blocks all CRU consumers, including the UART console,
leaving the system without a working console.
Would it be better to add a dummy frequency, mark these nodes with
status = "disabled" in the dtsi, or define them only at the board level
when they are actually present?
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260514-dr1v90-cru-v5-0-34f3021aab51@pigmoral.tech?part=5
next prev parent reply other threads:[~2026-05-14 19:48 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-14 9:27 [PATCH v5 0/6] clk/reset: anlogic: add support for DR1V90 SoC Junhui Liu
2026-05-14 9:27 ` [PATCH v5 1/6] clk: correct clk_div_mask() return value for width == 32 Junhui Liu
2026-05-14 18:22 ` sashiko-bot
2026-05-14 9:27 ` [PATCH v5 2/6] dt-bindings: clock: add Anlogic DR1V90 CRU Junhui Liu
2026-05-14 9:27 ` [PATCH v5 3/6] clk: anlogic: add cru support for Anlogic DR1V90 SoC Junhui Liu
2026-05-14 18:52 ` sashiko-bot
2026-05-14 9:27 ` [PATCH v5 4/6] reset: anlogic: add support for Anlogic DR1V90 resets Junhui Liu
2026-05-14 19:32 ` sashiko-bot
2026-05-14 9:27 ` [PATCH v5 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 Junhui Liu
2026-05-14 19:48 ` sashiko-bot [this message]
2026-05-14 9:27 ` [PATCH v5 6/6] MAINTAINERS: Add Anlogic DR1V90 CRU driver entry Junhui Liu
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