From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3077C17A2EA; Thu, 14 May 2026 21:02:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.171 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778792559; cv=none; b=rYjiu1vhjJIqhzJaDey1ZqFKDCCWsXYsCe/5lf0tw7TabYaiLQQBDgWmAwUmnXOMIeTnyihPobhQt4jG7yYUrqdAxRhxwAt+7WXjGWrPo8+Dv6L+E3qyAHcKgCXnpgFhgv2wSM9eIsL2v8kbmk7JBaSWK9RTaOlyO5PRx0NkJbw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778792559; c=relaxed/simple; bh=L6tgnJ6HVRpvyne7GS8JPqXSX4XQFaYBy7CWbE1jSv0=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=I+1ooWSaJzshe2RmFElZ3YXQn4pX6htPLnc3vsxp4p/Aj4dPGvDZY9Sw2L2oBfcyH1+BAIMIjH8YJqDaB0DIpmP1xw+VSlNW0mFtWG1fNCfiIbEDZOVP4yUwpU/+JN97CM7EA7vQSormSRA/JRuSAyT/GDnizmVnxjj6oPvnjPM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: fezz5zrPTDOd0v3OJeCDig== X-CSE-MsgGUID: WYp4g7/XRMW4GpD9CfKFOg== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 15 May 2026 06:02:27 +0900 Received: from mind-2s.lan (unknown [10.24.0.33]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 1E1AF40031EC; Fri, 15 May 2026 06:02:23 +0900 (JST) From: Fabrizio Castro To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Fabrizio Castro , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Subject: [PATCH v2] arm64: dts: renesas: rzt2h-n2h-evk: Configure eMMC/SDHI pins Date: Thu, 14 May 2026 22:02:17 +0100 Message-ID: <20260514210220.7616-1-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The HW user manual for the Renesas RZ/T2H and the RZ/N2H states that for SDR104, SDR50, and HS200 to work properly the eMMC/SDHI interface pins have to be configured as specified below: * SDn_CLK pin - drive strength: Ultra High, slew rate: Fast * Other SDn_* pins: drive strength: High, slew rate: Fast, Schmitt trigger: disabled (not applicable to SDn_RST pins). HS DDR and DDR50 are currently not supported, and for every other bus mode the eMMC/SDHI interface pins should be configured as specified below: * SDn_CLK pin - drive strength: High, slew rate: Fast * Other SDn_* pins: drive strength: Middle, slew rate: Fast, Schmitt trigger: disabled (not applicable to SDn_RST pins). Adjust the pin definitions accordingly. Signed-off-by: Fabrizio Castro --- v1->v2: * Take into account the settings for lower speed modes .../dts/renesas/rzt2h-n2h-evk-common.dtsi | 147 ++++++++++++++++-- 1 file changed, 136 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi index f87c2492f414..46f4aaac0478 100644 --- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi @@ -275,12 +275,63 @@ data-pins { , /* SD0_DATA5 */ , /* SD0_DATA6 */ ; /* SD0_DATA7 */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; }; - ctrl-pins { - pinmux = , /* SD0_CLK */ - , /* SD0_CMD */ - ; /* SD0_RST# */ + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + }; + + cmd-pins { + pinmux = ; /* SD0_CMD */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + rst-pins { + pinmux = ; /* SD0_RST# */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + }; + }; + + sdhi0_emmc_pins_uhs: sd0-emmc-group-uhs { + data-pins { + pinmux = , /* SD0_DATA0 */ + , /* SD0_DATA1 */ + , /* SD0_DATA2 */ + , /* SD0_DATA3 */ + , /* SD0_DATA4 */ + , /* SD0_DATA5 */ + , /* SD0_DATA6 */ + ; /* SD0_DATA7 */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; + + cmd-pins { + pinmux = ; /* SD0_CMD */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + rst-pins { + pinmux = ; /* SD0_RST# */ + drive-strength-microamp = <9000>; + slew-rate = <1>; }; }; @@ -299,12 +350,49 @@ data-pins { , /* SD0_DATA1 */ , /* SD0_DATA2 */ ; /* SD0_DATA3 */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <9000>; + slew-rate = <1>; }; ctrl-pins { - pinmux = , /* SD0_CLK */ - , /* SD0_CMD */ + pinmux = , /* SD0_CMD */ ; /* SD0_CD */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + }; + + sdhi0_sd_pins_uhs: sd0-sd-group-uhs { + data-pins { + pinmux = , /* SD0_DATA0 */ + , /* SD0_DATA1 */ + , /* SD0_DATA2 */ + ; /* SD0_DATA3 */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD0_CLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; + }; + + ctrl-pins { + pinmux = , /* SD0_CMD */ + ; /* SD0_CD */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; }; }; @@ -323,12 +411,49 @@ data-pins { , /* SD1_DATA1 */ , /* SD1_DATA2 */ ; /* SD1_DATA3 */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD1_CLK */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + }; + + ctrl-pins { + pinmux = , /* SD1_CMD */ + ; /* SD1_CD */ + drive-strength-microamp = <5000>; + slew-rate = <1>; + input-schmitt-disable; + }; + }; + + sdhi1_pins_uhs: sd1-group-uhs { + data-pins { + pinmux = , /* SD1_DATA0 */ + , /* SD1_DATA1 */ + , /* SD1_DATA2 */ + ; /* SD1_DATA3 */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; + }; + + clk-pins { + pinmux = ; /* SD1_CLK */ + drive-strength-microamp = <11800>; + slew-rate = <1>; }; ctrl-pins { - pinmux = , /* SD1_CLK */ - , /* SD1_CMD */ + pinmux = , /* SD1_CMD */ ; /* SD1_CD */ + drive-strength-microamp = <9000>; + slew-rate = <1>; + input-schmitt-disable; }; }; }; @@ -342,7 +467,7 @@ &sci0 { #if SD0_EMMC &sdhi0 { pinctrl-0 = <&sdhi0_emmc_pins>; - pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <®_1p8v>; @@ -357,7 +482,7 @@ &sdhi0 { #if SD0_SD &sdhi0 { pinctrl-0 = <&sdhi0_sd_pins>; - pinctrl-1 = <&sdhi0_sd_pins>; + pinctrl-1 = <&sdhi0_sd_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vqmmc_sdhi0>; @@ -372,7 +497,7 @@ &sdhi0 { #if SD1_MICRO_SD &sdhi1 { pinctrl-0 = <&sdhi1_pins>; - pinctrl-1 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <®_3p3v>; vqmmc-supply = <&vccq_sdhi1>; -- 2.34.1