From: sashiko-bot@kernel.org
To: "Jia Wang via B4 Relay" <devnull+wangjia.ultrarisc.com@kernel.org>
Cc: krzk+dt@kernel.org, robh@kernel.org, devicetree@vger.kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
Date: Fri, 15 May 2026 02:02:49 +0000 [thread overview]
Message-ID: <20260515020249.AAE16C2BCB3@smtp.kernel.org> (raw)
In-Reply-To: <20260515-ultrarisc-pinctrl-v1-5-bf559589ea8a@ultrarisc.com>
Thank you for your contribution! Sashiko AI review found 6 potential issue(s) to consider:
- [High] The `gpio-ranges` property values in `gpio_b`, `gpio_c`, and `gpio_d` incorrectly specify a local GPIO base that exceeds the available pins.
- [High] PCI I/O space is incorrectly mapped 1:1 to a high CPU address, breaking legacy PCI endpoints.
- [High] The Ethernet node incorrectly defines a broadcast MAC address as its local unicast MAC address.
- [Medium] Mismatch between CPU node unit addresses and their `reg` properties.
- [Medium] Ethernet compatible strings are listed in the wrong order.
- [Low] Clock node names contain underscores instead of hyphens.
--
commit f5aec289ca4daa2ae7f4c27bac4b1694ece4043b
Author: Jia Wang <wangjia@ultrarisc.com>
riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000
Add the base device tree for the UltraRISC DP1000 SoC. It describes the
8×CP100 CPU cores and essential SoC peripherals including the interrupt
controller, pinctrl, GPIO, UART, SPI, I2C, PCIe, GMAC and the DMA
controller.
Link: https://lore.kernel.org/lkml/20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com/
Link: https://lore.kernel.org/lkml/20260429-ultrarisc-serial-v7-3-e475cce9e274@ultrarisc.com/
> diff --git a/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
> new file mode 100644
> index 0000000000000..1aae53fc1a2b1
> --- /dev/null
> +++ b/arch/riscv/boot/dts/ultrarisc/dp1000.dtsi
> @@ -0,0 +1,851 @@
[ ... ]
> + cpu4: cpu@4 {
> + compatible = "ultrarisc,cp100", "riscv";
> + reg = <0x10>;
Does the unit address in the node name here correctly match the first
address specified in its reg property?
The Devicetree Specification mandates that the hexadecimal value after the @
must exactly match the reg value to avoid parser errors and dtc compiler
warnings. Should these be renamed to cpu@10, cpu@11, cpu@12, and cpu@13?
[ ... ]
> + clocks {
> + device_clk: device_clk {
Is it intended to use underscores in these clock node names?
Device tree naming conventions generally require node names to use hyphens
instead of underscores (e.g., device-clk) to avoid triggering strict
character warnings.
[ ... ]
> + gpio_b: gpio-port@1 {
> + compatible = "snps,dw-apb-gpio-port";
> + reg = <1>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + snps,nr-gpios = <8>;
> + gpio-ranges = <&pmx0 16 0 8>;
Will operations on local GPIOs 0-7 have a valid pinmux mapping with this
configuration?
The gpio-ranges property uses the format <pinctrl_phandle gpio_base
pinctrl_base count>. By specifying a local gpio_base of 16 for a port with
only 8 pins, it seems gpiolib will fail to configure pins 0-7 correctly.
Should this be inverted to <&pmx0 0 16 8> to map local GPIOs 0-7 to
pinctrl pins 16-23? This appears to be similarly configured for gpio_c and
gpio_d as well.
[ ... ]
> + pcie_x16: pcie@21000000 {
> + compatible = "ultrarisc,dp1000-pcie";
> + reg = <0x0 0x21000000 0x0 0x01000000>,
> + <0x0 0x4fff0000 0x0 0x00010000>;
> + reg-names = "dbi", "config";
> + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,
Can legacy PCI endpoints and HBAs that only decode 16-bit I/O addresses
successfully initialize with this mapping?
The ranges property maps the CPU MMIO address 0x4fbf0000 directly to the
PCI bus I/O address 0x4fbf0000 (indicated by the 0x81000000 bitfield).
Would it be better to map the CPU MMIO region to a PCI bus I/O address of 0
instead?
[ ... ]
> + ethernet: ethernet@38000000 {
> + compatible = "snps,dwmac", "snps,dwmac-5.10a";
Could the OS prematurely bind to the generic driver before applying
hardware-specific driver quirks with this ordering? Device tree bindings
typically require the compatible array to be ordered from most specific to
least specific.
> + reg = <0x00 0x38000000 0x00 0x1000000>;
> + clocks = <&csr_clk>;
> + clock-names = "stmmaceth";
> + interrupt-parent = <&plic>;
> + interrupts = <84>;
> + interrupt-names = "macirq";
> + local-mac-address = [ff ff ff ff ff ff];
Will the network driver initialize with an invalid broadcast MAC address if
the bootloader does not dynamically overwrite this value?
Using a broadcast address as a source MAC violates IEEE 802.3 standards,
and upstream network switches may drop packets sent by this interface.
Should this be omitted or zeroed out as a placeholder?
> + max-speed = <1000>;
> + phy-mode = "rgmii-id";
> + snps,txpbl = <8>;
> + snps,rxpbl = <8>;
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-ultrarisc-pinctrl-v1-0-bf559589ea8a@ultrarisc.com?part=5
next prev parent reply other threads:[~2026-05-15 2:02 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 1:17 [PATCH 0/9] riscv: ultrarisc: add DP1000 SoC DT and pinctrl support Jia Wang via B4 Relay
2026-05-15 1:17 ` [PATCH 1/9] dt-bindings: vendor-prefixes: add Rongda Jia Wang via B4 Relay
2026-05-15 1:20 ` sashiko-bot
2026-05-15 1:25 ` Jia Wang
2026-05-15 1:17 ` [PATCH 2/9] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-05-15 1:17 ` [PATCH 3/9] dt-bindings: riscv: Add UltraRISC DP1000 bindings Jia Wang via B4 Relay
2026-05-15 1:18 ` [PATCH 4/9] dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl bindings Jia Wang via B4 Relay
2026-05-15 1:49 ` sashiko-bot
2026-05-15 1:18 ` [PATCH 5/9] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-05-15 2:02 ` sashiko-bot [this message]
2026-05-15 1:18 ` [PATCH 6/9] pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver Jia Wang via B4 Relay
2026-05-15 2:28 ` sashiko-bot
2026-05-15 1:18 ` [PATCH 7/9] riscv: dts: ultrarisc: add Rongda M0 board device tree Jia Wang via B4 Relay
2026-05-15 2:37 ` sashiko-bot
2026-05-15 1:18 ` [PATCH 8/9] riscv: dts: ultrarisc: add Milk-V Titan " Jia Wang via B4 Relay
2026-05-15 2:50 ` sashiko-bot
2026-05-15 1:18 ` [PATCH 9/9] riscv: defconfig: enable ARCH_ULTRARISC Jia Wang via B4 Relay
2026-05-15 2:59 ` sashiko-bot
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260515020249.AAE16C2BCB3@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=devnull+wangjia.ultrarisc.com@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=robh@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox