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The sensors are connected via I2C1 and I2C2, each with proper endpoint descriptions to form complete media pipelines. The resulting pipelines are: - OV5640 (I2C2) -> MIPI CSI1 -> CSI1 bridge - OV5640 (I2C1) -> MIPI CSI2 -> CSI2 bridge Both pipelines have been validated on the i.MX8MQ EVK using the upstream OV5640 driver. Both OV5640 sensors share a single reset GPIO on this board, which prevents independent hardware reset when both cameras are enabled. As a result, the reset line is kept deasserted via a GPIO hog, and sensor reset is performed via software. This reflects a hardware limitation of the i.MX8MQ EVK design, which does not provide independent reset control for the two image sensors. Both sensors also share a single MCLK source (CLKO2). The clock is configured identically for both devices to match the board design. Signed-off-by: Robby Cai --- Changes in v2: - Address comments on MIPI clock configuration (Frank, Sebastian): drop the first patch and consolidate the correct clock configuration into the second patch - Address comments from sashiko: * Use MEDIA_BUS_TYPE_CSI2_DPHY instead of a literal value * Fix a probe-order dependency related to reset handling. Switch to software reset, as the shared hardware reset line prevents independent reset when both cameras are enabled due to a board design limitation * Fix incorrect voltage value in the reg_2v8 node Link to v1: https://lore.kernel.org/imx/20260417110200.753678-1-robby.cai@nxp.com/ Note: This patch relies on commit 6d79bb8fd2aa ("media: imx8mq-mipi-csi2: Explicitly release reset") and patch [1]. These two changes are interdependent and must be applied together for correct behavior. Applying only one of them is insufficient and may result in incorrect operation. [1] https://lore.kernel.org/imx/20260417080851.489303-1-robby.cai@nxp.com/ Validated with following commands: On CSI1: media-ctl -d 0 -l "'ov5640 1-003c':0 -> 'imx8mq-mipi-csi2 30a70000.csi':0 [1]" media-ctl -d 0 -V "'ov5640 1-003c':0 [fmt:YUYV8_1X16/640x480 field:none]" media-ctl -d 0 -V "'imx8mq-mipi-csi2 30a70000.csi':0 [fmt:YUYV8_1X16/640x480 field:none]" media-ctl -d 0 -V "'csi':0 [fmt:YUYV8_1X16/640x480 field:none]" v4l2-ctl -d 0 --set-fmt-video=width=640,height=480,pixelformat=YUYV --stream-mmap On CSI2: media-ctl -d 1 -l "'ov5640 0-003c':0 -> 'imx8mq-mipi-csi2 30b60000.csi':0 [1]" media-ctl -d 1 -V "'ov5640 0-003c':0 [fmt:YUYV8_1X16/640x480 field:none]" media-ctl -d 1 -V "'imx8mq-mipi-csi2 30b60000.csi':0 [fmt:YUYV8_1X16/640x480 field:none]" media-ctl -d 1 -V "'csi':0 [fmt:YUYV8_1X16/640x480 field:none]" v4l2-ctl -d 1 --set-fmt-video=width=640,height=480,pixelformat=YUYV --stream-mmap --- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 165 +++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts index d48f901487d4..2311a05b88c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts @@ -6,6 +6,8 @@ /dts-v1/; +#include + #include "imx8mq.dtsi" / { @@ -50,6 +52,20 @@ reg_usdhc2_vmmc: regulator-vsd-3v3 { enable-active-high; }; + reg_1v5: regulator-1v5 { + compatible = "regulator-fixed"; + regulator-name = "DVDD_1V5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + reg_2v8: regulator-2v8 { + compatible = "regulator-fixed"; + regulator-name = "AVDD_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + buck2_reg: regulator-buck2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_buck2>; @@ -172,6 +188,14 @@ &A53_3 { cpu-supply = <&buck2_reg>; }; +&csi1 { + status = "okay"; +}; + +&csi2 { + status = "okay"; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; status = "okay"; @@ -230,6 +254,19 @@ vddh: vddh-regulator { }; }; +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera_reset>; + + /* deasserted: logical 0 -> physical 1 via ACTIVE_LOW */ + camera-reset-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "camera-reset"; + }; +}; + &gpio5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_reset>; @@ -330,12 +367,101 @@ vgen6_reg: vgen6 { }; }; }; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera2_pwdn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + powerdown-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + DOVDD-supply = <&sw4_reg>; + AVDD-supply = <®_2v8>; + DVDD-supply = <®_1v5>; + + port { + camera2_ep: endpoint { + remote-endpoint = <&mipi_csi2_in_ep>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera1_pwdn>; + clocks = <&clk IMX8MQ_CLK_CLKO2>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; + assigned-clock-rates = <20000000>; + powerdown-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + DOVDD-supply = <&sw4_reg>; + AVDD-supply = <®_2v8>; + DVDD-supply = <®_1v5>; + + port { + camera1_ep: endpoint { + remote-endpoint = <&mipi_csi1_in_ep>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &lcdif { status = "okay"; }; +&mipi_csi1 { + assigned-clock-rates = <266000000>, <200000000>, <66000000>; + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi_csi1_in_ep: endpoint { + remote-endpoint = <&camera1_ep>; + data-lanes = <1 2>; + bus-type = ; + }; + }; + }; +}; + +&mipi_csi2 { + assigned-clock-rates = <266000000>, <200000000>, <66000000>; + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi_csi2_in_ep: endpoint { + remote-endpoint = <&camera2_ep>; + data-lanes = <1 2>; + bus-type = ; + }; + }; + }; +}; + &mipi_dsi { #address-cells = <1>; #size-cells = <0>; @@ -532,12 +658,37 @@ &wdog1 { }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mclk>; + pinctrl_buck2: vddarmgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 >; }; + pinctrl_camera1_pwdn: camera1pwdngrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + >; + }; + + pinctrl_camera2_pwdn: camera2pwdngrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + >; + }; + + /* + * Shared reset line for cameras on CSI1 and CSI2. + * Configured as GPIO and held high; sensors rely on software reset. + */ + pinctrl_camera_reset: cameraresetgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -565,12 +716,26 @@ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + pinctrl_ir: irgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f >; }; + /* Shared MCLK for cameras on CSI1 and CSI2. */ + pinctrl_mclk: mclkgrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 + >; + }; + pinctrl_mipi_dsi: mipidsigrp { fsl,pins = < MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16 -- 2.37.1