From: sashiko-bot@kernel.org
To: "Ioana Ciornei" <ioana.ciornei@nxp.com>
Cc: conor+dt@kernel.org, krzk+dt@kernel.org,
devicetree@vger.kernel.org, linux-phy@lists.infradead.org,
olteanv@gmail.com, neil.armstrong@linaro.org, vkoul@kernel.org,
robh@kernel.org
Subject: Re: [PATCH v2 phy-next 2/2] phy: ti: add PHY driver for TI DS125DF111 Dual-Channel Retimer
Date: Fri, 15 May 2026 11:22:52 +0000 [thread overview]
Message-ID: <20260515112252.E684CC2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260515110145.1925579-3-ioana.ciornei@nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing delay or polling after setting a self-clearing hardware reset bit.
--
commit 59a5ca7411308a81c146d660b8c04e0be8fe8fbb
Author: Ioana Ciornei <ioana.ciornei@nxp.com>
phy: ti: add PHY driver for TI DS125DF111 Dual-Channel Retimer
This commit adds a generic PHY driver for the TI DS125DF111 Multi-Protocol
Dual-Channel Retimer. It supports 10G and 1G link speeds, modeling each of
the two channels as a separate PHY device.
> diff --git a/drivers/phy/ti/phy-ds125df111.c b/drivers/phy/ti/phy-ds125df111.c
> new file mode 100644
> --- /dev/null
> +++ b/drivers/phy/ti/phy-ds125df111.c
[ ... ]
> +static int ds125df111_configure(struct phy *phy,
> + const struct ds125df111_config *cfg)
> +{
[ ... ]
> + /* Reset Channel Registers */
> + err = i2c_smbus_read_byte_data(i2c, DS125DF111_CH_CTRL);
> + if (err < 0) {
> + dev_err(dev, "Error resetting channel configuration\n");
> + goto out;
> + }
> + val = (u8)err;
> + val |= DS125DF111_CH_CTRL_RESET;
> + err = i2c_smbus_write_byte_data(i2c, DS125DF111_CH_CTRL, val);
> + if (err < 0) {
> + dev_err(dev, "Error resetting channel configuration\n");
> + goto out;
> + }
> +
> + /* Program the VCO group frequencies */
> + for (i = 0; i < DS125DF111_NUM_VCO_GROUP_REG; i++) {
> + err = i2c_smbus_write_byte_data(i2c,
> + DS125DF111_VCO_GROUP_BASE + i,
> + cfg->vco_group[i]);
Is a delay or polling loop needed after triggering the channel reset?
The DS125DF111_CH_CTRL_RESET bit is defined as self-clearing, but the code
immediately proceeds to program the VCO group frequencies without checking if
the reset has finished.
Since hardware resets usually take a non-zero amount of time, writing to the
registers right away could result in the device NACKing the transactions or
silently dropping the new configuration.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515110145.1925579-1-ioana.ciornei@nxp.com?part=2
next prev parent reply other threads:[~2026-05-15 11:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 11:01 [PATCH v2 phy-next 0/2] phy: ti: add driver for TI DS125DF111 Dual-Channel Retimer Ioana Ciornei
2026-05-15 11:01 ` [PATCH v2 phy-next 1/2] dt-bindings: phy: add PHY bindings for the TI DS125DF111 Retimer PHY Ioana Ciornei
2026-05-15 11:01 ` [PATCH v2 phy-next 2/2] phy: ti: add PHY driver for TI DS125DF111 Dual-Channel Retimer Ioana Ciornei
2026-05-15 11:22 ` sashiko-bot [this message]
2026-05-15 14:36 ` Ioana Ciornei
2026-05-15 12:24 ` Vladimir Oltean
2026-05-15 13:44 ` Ioana Ciornei
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