From: sashiko-bot@kernel.org
To: "Aaron Kling via B4 Relay" <devnull+webgeek1234.gmail.com@kernel.org>
Cc: robh@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org,
conor+dt@kernel.org
Subject: Re: [PATCH 1/3] spi: dt-bindings: tegra: Support IOMMU property for Tegra194 QSPI
Date: Fri, 15 May 2026 20:43:31 +0000 [thread overview]
Message-ID: <20260515204332.13C20C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260515-tegra194-qspi-iommu-v1-1-57dfb63cd3d6@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Incorrectly allowing the `iommus` property on a device node that uses an external DMA controller.
--
commit 7b9b9a70107dbc216f12066e863bde3029e71a0d
Author: Aaron Kling <webgeek1234@gmail.com>
spi: dt-bindings: tegra: Support IOMMU property for Tegra194 QSPI
This commit updates the Tegra210 QSPI device tree binding to allow the
iommus property for the Tegra194 QSPI compatible string. It states that
this is supported via an external DMA controller.
> spi: dt-bindings: tegra: Support IOMMU property for Tegra194 QSPI
>
> This is supported via an external dma controller
If the Tegra194 QSPI controller uses an external DMA controller, the external
DMA controller acts as the bus master while the QSPI controller is a peripheral
slave. Because the iommus property specifies the IOMMU master interfaces for a
device that performs direct memory access, does this property belong on the
external DMA controller's node rather than the QSPI controller's node?
> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> --- a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> @@ -78,7 +78,9 @@ allOf:
> compatible:
> not:
> contains:
> - const: nvidia,tegra234-qspi
> + enum:
> + - nvidia,tegra194-qspi
> + - nvidia,tegra234-qspi
> then:
> properties:
> iommus: false
Allowing the iommus property on the QSPI node here appears to misrepresent
the hardware architecture for an external DMA topology. If the operating
system attempts to attach an IOMMU domain to the QSPI device based on
this binding, could the actual DMA transfers fault due to the DMA controller
itself not being mapped?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-tegra194-qspi-iommu-v1-0-57dfb63cd3d6@gmail.com?part=1
next prev parent reply other threads:[~2026-05-15 20:43 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-15 20:35 [PATCH 0/3] arm64: tegra: Add iommu and dma properties for Tegra194 QSPI Aaron Kling via B4 Relay
2026-05-15 20:35 ` [PATCH 1/3] spi: dt-bindings: tegra: Support IOMMU property " Aaron Kling via B4 Relay
2026-05-15 20:43 ` sashiko-bot [this message]
2026-05-15 20:35 ` [PATCH 2/3] spi: dt-bindings: tegra: Support dma-coherent property for QSPI Aaron Kling via B4 Relay
2026-05-15 20:51 ` sashiko-bot
2026-05-15 20:35 ` [PATCH 3/3] arm64: tegra: Add iommu and dma properties for Tegra194 QSPI Aaron Kling via B4 Relay
2026-05-15 21:17 ` sashiko-bot
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