Re: [PATCH v5] arm64: dts: imx95: Correct PCIe outbound address space configuration

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The PCI child bus address for the I/O space is incorrectly set to 0xf0000000, which breaks devices that rely on 16-bit I/O addressing.
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commit ce14f8afc3b0f35c82afa68f19826408baa01125
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx95: Correct PCIe outbound address space configuration

This commit updates the PCIe outbound memory ranges for pcie0 and pcie1
on i.MX95 to expand the memory window from 256MB to roughly 3840MB. It
also relocates the 1MB I/O region to immediately follow the memory region.

> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index adcc0e1d3696b..c43f2bec99d0a 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1939,8 +1939,8 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c360000 0 0x10000>,
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
> -			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> -				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> +			ranges = <0x82000000 0x0 0x00000000 0x9 0x00000000 0x0 0xf0000000>,
> +				 <0x81000000 0x0 0xf0000000 0x9 0xf0000000 0x0 0x00100000>;

Will setting the PCI child bus address for the I/O space to 0xf0000000
cause issues for devices that rely on 16-bit I/O addressing?

The previous configuration used a PCI bus address of 0x00000000. While the
parent CPU address is correctly offset to 0x9_f0000000, applying the same
offset to the child PCI address forces the Linux PCI core to allocate I/O
ports starting at 0xf0000000 on the PCI bus.

Many legacy PCIe endpoint devices and PCI-to-PCI bridges only decode
16-bit I/O addresses up to 0xffff. Assigning an I/O base address of
0xf0000000 could cause allocations to conflict or fail completely for
these devices.

Should the child PCI address for the I/O ranges remain 0x0 0x00000000?

[ ... ]

> @@ -2014,8 +2014,8 @@ pcie1: pcie@4c380000 {
>  			      <0 0x4c3e0000 0 0x10000>,
>  			      <0 0x4c3c0000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
> -			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
> -				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
> +			ranges = <0x82000000 0x0 0x00000000 0xa 0x00000000 0x0 0xf0000000>,
> +				 <0x81000000 0x0 0xf0000000 0xa 0xf0000000 0x0 0x00100000>;

This has the same child I/O bus address concern as pcie0 above. Could this
also be updated to use 0x0 0x00000000 for the child PCI address?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260519022220.57686-1-hongxing.zhu@nxp.com?part=1