From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB8DC3DCDBF for ; Tue, 19 May 2026 07:47:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.117.254.33 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779176846; cv=none; b=LBi/cAM4cR4si/fyonQoM8+fQ9pf6tJcWUG4/u0cr6Ln/1Tp+VcAd/AFVKopvst2ieA4e2ek/4l0onLVHt/RUigZYNFoaVN0OMm7+750zaqo8den02I8x8idPx32NMQxZYVlLzezqSfPR67CdEJ8yzDdIZzNrkTZB8pcajCI4LE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779176846; c=relaxed/simple; bh=JFOj2pTcr1NCSC8rxSCD8rWDK53DtBnwrWIW1y5v3j0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ulMPyxIaSxFnVzNhKvSEFF2cv+8fhaBFBF1O1skv8QmhcuZPrVAZLg2V7cD1M7gIcsdMvm5RolOf+voA4eEcwdc4iitY9KQ+MmkBGI3MGF74rGI6v8erEEH+PAVFJCPRsxnDhIvKg+SjMQ0yPlwnXtiqRpKwpKJQlj8XzI/U2zU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b=lqWVe1f7; arc=none smtp.client-ip=194.117.254.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sang-engineering.com header.i=@sang-engineering.com header.b="lqWVe1f7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; s=k1; bh=wUpTJzvvS6yimETraOlYVE2+3FX9+pfKlsyxLhI6Auc=; b=lqWVe1 f7ydvidKRi+ZPLbP12C+xP75D34lip7Pwx4kNMwS1EcgsJ61ypgNgHFQniKA75E3 RA1B/mkoB9JTU8nuUkGcAp9l8vrB3kwFWMusn8STbZhSBOXuAKjTGw6bZtIMhaXk 09+XQZsMYUC2pfMhBa+0s80H0aORLxcp+JkIcwFl6ncCSron9MP3Ni+HJb6vL+H6 FIaGezX9wJHp/y+Yff8Bn8Z3cLRu1AQitSb8T4yZbpe+oYeSxOLcNCwYoMfXN65G Vx4rb7E1sjb371dxQ3VeGU+JA3xCPpFCamQDf4KB6qOQb0E94HIn9Gb6BhfnydCE a043Inu+0+Pccchw== Received: (qmail 167973 invoked from network); 19 May 2026 09:47:13 +0200 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 19 May 2026 09:47:13 +0200 X-UD-Smtp-Session: l3s3148p1@kEgl4yZS4CJUszca From: Wolfram Sang To: linux-renesas-soc@vger.kernel.org Cc: Kuninori Morimoto , Vinh Nguyen , Hai Pham , Wolfram Sang , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org Subject: [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes Date: Tue, 19 May 2026 09:47:03 +0200 Message-ID: <20260519074702.3308-5-wsa+renesas@sang-engineering.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260519074702.3308-4-wsa+renesas@sang-engineering.com> References: <20260519074702.3308-4-wsa+renesas@sang-engineering.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Kuninori Morimoto Describe the MFIS and MFIS SCP instances which are used for various tasks including inter-processor communication. Remove the PRR node because it is part of MFIS on R-Car X5H and should be handled using the MFIS compatible. Also, describe the STCM transport area used for shared memory mailboxing. Signed-off-by: Vinh Nguyen Signed-off-by: Hai Pham Signed-off-by: Kuninori Morimoto Signed-off-by: Wolfram Sang --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 129 +++++++++++++++++++++- 1 file changed, 126 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 3ec1b53d2782..3509d29bfdd8 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -678,9 +678,123 @@ soc: soc { #size-cells = <2>; ranges; - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; + mfis: system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #mbox-cells = <2>; + #hwlock-cells = <1>; + status = "disabled"; + }; + + mfis_scp: system-controller@189e1000 { + compatible = "renesas,r8a78000-mfis-scp"; + reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + /* SCP uses I side IRQ only */ + interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i", + "ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i", + "ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i", + "ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i"; + #mbox-cells = <2>; + #hwlock-cells = <1>; + status = "disabled"; }; /* Application Processors manage View-1 of a GIC-720AE */ @@ -773,6 +887,15 @@ hscif3: serial@c071c000 { clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; + + stcm_transport: sram@c1060000 { + compatible = "mmio-sram"; + reg = <0x0 0xc1060000 0x0 0x1c00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1060000 0x1c00>; + /* actual transport nodes must be set per board file */ + }; }; timer { -- 2.51.0