Re: [PATCH v5] arm64: dts: qcom: glymur: add coresight nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The `tn@11200000` node violates the `qcom,coresight-itnoc` device tree binding schema.
--

commit 30295a9238dfaa7e7f3c2a597e85a52b878ac32f
Author: Jie Gan <jie.gan@oss.qualcomm.com>

arm64: dts: qcom: glymur: add coresight nodes

This commit adds CoreSight nodes to enable trace paths like TPDM->ETF/STM->ETF
on the Glymur platform. It also deletes the cti_wpss DT node on Mahua since it
will cause NoC issues.

> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 0c5cb8532b202..a606235bdb4b1 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
[ ... ]
> +		tn@11200000  {
> +			compatible = "qcom,coresight-itnoc";
> +			reg = <0x0 0x11200000 0x0 0x3c00>;
> +
> +			clocks = <&aoss_qmp>;
> +			clock-names = "apb_pclk";

Does the node name tn@11200000 violate the qcom,coresight-itnoc device tree
binding schema? The schema requires the node name to match the pattern
^itnoc(@[0-9a-f]+)?$.

Additionally, does the clock-names property value "apb_pclk" violate the
schema which strictly expects "apb"?

While the coresight clock parsing logic gracefully accepts "apb_pclk" and
falls back to "apb" avoiding a runtime failure, this mismatch will cause
new make dtbs_check validation errors.

> +
> +			in-ports {
> +				#address-cells = <1>;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260519-add-coresight-nodes-for-glymur-v5-1-3dad99fe31e0@oss.qualcomm.com?part=1