Re: [PATCH v7] arm64: dts: imx95: Correct PCIe outbound address space configuration

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The 32-bit non-prefetchable memory region is mapped to PCI bus address 0x00000000, which breaks identity mapping, risks BAR allocation at 0x0, and causes inbound DMA routing conflicts with low IOVAs.
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commit e0f5ac7bad631db9fb55f3b3093d93a9bac757ae
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx95: Correct PCIe outbound address space configuration

This commit fixes the PCIe outbound memory ranges for both pcie0 and pcie1
controllers on i.MX95 by expanding the outbound address space window size.
It also relocates the 1MB I/O region to use a memory-mapped region instead
of I/O space.

> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 71394871d8dd0..2c058f6105550 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1852,8 +1852,9 @@ pcie0: pcie@4c300000 {

[ ... ]

> -			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> -				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> +			ranges = <0x43000000 0x9 0x00000000 0x9 0x00000000 0x0 0xe0000000>,
> +				 <0x82000000 0x0 0x00000000 0x9 0xe0000000 0x0 0x10000000>,

[Severity: High]
Does mapping the 32-bit non-prefetchable memory region to PCI bus address
0x00000000 break identity mapping and risk inbound DMA routing conflicts?

By assigning the PCI base address to 0x0, the PCIe Root Port's Type 1
configuration space will be programmed with a Memory Base of 0x0. If a
downstream device initiates inbound DMA to system RAM using an IOMMU-assigned
IOVA that falls within this low address range, the Root Port might interpret
the transaction as a peer-to-peer access.

Could this cause the transaction to be routed back downstream to the PCIe
bus instead of being forwarded upstream to the system bus and IOMMU? To
prevent this, should the PCI address be set to a high non-zero value, such
as 0xe0000000, matching the lower 32 bits of the CPU address?

> +				 <0x81000000 0x0 0x00000000 0x9 0xf0000000 0x0 0x00100000>;
>  			#address-cells = <3>;

[ ... ]

> @@ -1927,8 +1928,9 @@ pcie1: pcie@4c380000 {

[ ... ]

> -			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
> -				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
> +			ranges = <0x43000000 0xa 0x00000000 0xa 0x00000000 0x0 0xe0000000>,
> +				 <0x82000000 0x0 0x00000000 0xa 0xe0000000 0x0 0x10000000>,

[Severity: High]
Will this have the same DMA routing conflict with low IOVAs as the pcie0
controller above, since it is also mapped to PCI bus address 0x00000000?

> +				 <0x81000000 0x0 0x00000000 0xa 0xf0000000 0x0 0x00100000>;
>  			#address-cells = <3>;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260520035642.2207511-1-hongxing.zhu@nxp.com?part=1