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From: sashiko-bot@kernel.org
To: "Drew Fustini" <fustini@kernel.org>
Cc: devicetree@vger.kernel.org, conor+dt@kernel.org, robh@kernel.org
Subject: Re: [PATCH v2] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU
Date: Wed, 20 May 2026 06:37:29 +0000	[thread overview]
Message-ID: <20260520063729.AB98D1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260520061855.1623468-4-fustini@kernel.org>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing Schema Constraints for Hardware Variant
--

commit 171e0844b229701117691d7ea692a719866e79d9
Author: Nicholas Piggin <npiggin@gmail.com>

dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

This commit extends the RISC-V IOMMU binding to cover the Tenstorrent
variant. It adds a second register range for machine-mode (M-privileged)
registers such as PMAs and PMPs.

> diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml

[ ... ]

> @@ -75,6 +88,31 @@ required:
>  
>  additionalProperties: false
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - tenstorrent,riscv-iommu
> +    then:
> +      properties:
> +        reg:
> +          items:
> +            - description: IOMMU base registers
> +            - description: Tenstorrent IOMMU machine mode registers.
> +        reg-names:
> +          items:
> +            - const: base
> +            - const: machine
> +              description:
> +                Region containing platform specific MMRs for machine-mode
> +                configuration, such as PMA and PMP registers.

[Severity: Medium]
Should minItems: 2 be explicitly specified for the reg property in this
block?

Since the top-level schema allows minItems: 1, a device tree could
provide only a single register range and silently pass validation if
the tooling does not automatically infer the minimum items from the items
list within the conditional block.

Additionally, since the Tenstorrent variant introduces a second distinct
register region, should reg-names be added to a required list within this
conditional block to guarantee the regions are always properly disambiguated
by software?

> +    else:
> +      properties:
> +        reg:
> +          maxItems: 1

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260520061855.1623468-4-fustini@kernel.org?part=1

      reply	other threads:[~2026-05-20  6:37 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-20  6:16 [PATCH v2] dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU Drew Fustini
2026-05-20  6:37 ` sashiko-bot [this message]

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